@@ -132,13 +132,21 @@ enum i40e_admin_queue_opc {
132132 i40e_aqc_opc_list_func_capabilities = 0x000A ,
133133 i40e_aqc_opc_list_dev_capabilities = 0x000B ,
134134
135+ /* Proxy commands */
136+ i40e_aqc_opc_set_proxy_config = 0x0104 ,
137+ i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105 ,
138+
135139 /* LAA */
136140 i40e_aqc_opc_mac_address_read = 0x0107 ,
137141 i40e_aqc_opc_mac_address_write = 0x0108 ,
138142
139143 /* PXE */
140144 i40e_aqc_opc_clear_pxe_mode = 0x0110 ,
141145
146+ /* WoL commands */
147+ i40e_aqc_opc_set_wol_filter = 0x0120 ,
148+ i40e_aqc_opc_get_wake_reason = 0x0121 ,
149+
142150 /* internal switch commands */
143151 i40e_aqc_opc_get_switch_config = 0x0200 ,
144152 i40e_aqc_opc_add_statistics = 0x0201 ,
@@ -177,6 +185,7 @@ enum i40e_admin_queue_opc {
177185 i40e_aqc_opc_remove_control_packet_filter = 0x025B ,
178186 i40e_aqc_opc_add_cloud_filters = 0x025C ,
179187 i40e_aqc_opc_remove_cloud_filters = 0x025D ,
188+ i40e_aqc_opc_clear_wol_switch_filters = 0x025E ,
180189
181190 i40e_aqc_opc_add_mirror_rule = 0x0260 ,
182191 i40e_aqc_opc_delete_mirror_rule = 0x0261 ,
@@ -563,6 +572,56 @@ struct i40e_aqc_clear_pxe {
563572
564573I40E_CHECK_CMD_LENGTH (i40e_aqc_clear_pxe );
565574
575+ /* Set WoL Filter (0x0120) */
576+
577+ struct i40e_aqc_set_wol_filter {
578+ __le16 filter_index ;
579+ #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
580+ #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
581+ #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
582+ I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
583+
584+ #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
585+ #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
586+ I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
587+ __le16 cmd_flags ;
588+ #define I40E_AQC_SET_WOL_FILTER 0x8000
589+ #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
590+ #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
591+ #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
592+ __le16 valid_flags ;
593+ #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
594+ #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
595+ u8 reserved [2 ];
596+ __le32 address_high ;
597+ __le32 address_low ;
598+ };
599+
600+ I40E_CHECK_CMD_LENGTH (i40e_aqc_set_wol_filter );
601+
602+ struct i40e_aqc_set_wol_filter_data {
603+ u8 filter [128 ];
604+ u8 mask [16 ];
605+ };
606+
607+ I40E_CHECK_STRUCT_LEN (0x90 , i40e_aqc_set_wol_filter_data );
608+
609+ /* Get Wake Reason (0x0121) */
610+
611+ struct i40e_aqc_get_wake_reason_completion {
612+ u8 reserved_1 [2 ];
613+ __le16 wake_reason ;
614+ #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
615+ #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
616+ I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
617+ #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
618+ #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
619+ I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
620+ u8 reserved_2 [12 ];
621+ };
622+
623+ I40E_CHECK_CMD_LENGTH (i40e_aqc_get_wake_reason_completion );
624+
566625/* Switch configuration commands (0x02xx) */
567626
568627/* Used by many indirect commands that only pass an seid and a buffer in the
@@ -645,6 +704,8 @@ struct i40e_aqc_set_port_parameters {
645704#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
646705#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
647706 __le16 bad_frame_vsi ;
707+ #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
708+ #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
648709 __le16 default_seid ; /* reserved for command */
649710 u8 reserved [10 ];
650711};
@@ -696,6 +757,7 @@ I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
696757/* Set Switch Configuration (direct 0x0205) */
697758struct i40e_aqc_set_switch_config {
698759 __le16 flags ;
760+ /* flags used for both fields below */
699761#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
700762#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
701763 __le16 valid_flags ;
@@ -1844,11 +1906,12 @@ struct i40e_aqc_get_link_status {
18441906#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
18451907#define I40E_AQ_CONFIG_CRC_ENA 0x04
18461908#define I40E_AQ_CONFIG_PACING_MASK 0x78
1847- u8 external_power_ability ;
1909+ u8 power_desc ;
18481910#define I40E_AQ_LINK_POWER_CLASS_1 0x00
18491911#define I40E_AQ_LINK_POWER_CLASS_2 0x01
18501912#define I40E_AQ_LINK_POWER_CLASS_3 0x02
18511913#define I40E_AQ_LINK_POWER_CLASS_4 0x03
1914+ #define I40E_AQ_PWR_CLASS_MASK 0x03
18521915 u8 reserved [4 ];
18531916};
18541917
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