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Konrad Dybciorobclark
Konrad Dybcio
authored and
robclark
committed
drm/msm/adreno: Add A619 support
Add support for the Adreno 619 GPU, as found in Snapdragon 690 (SM6350), 480 (SM4350) and 750G (SM7225). Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/487588/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Clark <[email protected]>
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‎drivers/gpu/drm/msm/adreno/a6xx_gmu.c‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -528,6 +528,8 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
528528
pdc_in_aop = true;
529529
else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))
530530
pdc_address_offset = 0x30090;
531+
else if (adreno_is_a619(adreno_gpu))
532+
pdc_address_offset = 0x300a0;
531533
else
532534
pdc_address_offset = 0x30080;
533535

@@ -602,7 +604,8 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
602604

603605
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
604606
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
605-
if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
607+
if (adreno_is_a618(adreno_gpu) || adreno_is_a619(adreno_gpu) ||
608+
adreno_is_a650_family(adreno_gpu))
606609
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
607610
else
608611
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
@@ -1538,6 +1541,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
15381541
SZ_16M - SZ_16K, 0x04000, "icache");
15391542
if (ret)
15401543
goto err_memory;
1544+
/*
1545+
* NOTE: when porting legacy ("pre-650-family") GPUs you may be tempted to add a condition
1546+
* to allocate icache/dcache here, as per downstream code flow, but it may not actually be
1547+
* necessary. If you omit this step and you don't get random pagefaults, you are likely
1548+
* good to go without this!
1549+
*/
15411550
} else if (adreno_is_a640_family(adreno_gpu)) {
15421551
ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
15431552
SZ_256K - SZ_16K, 0x04000, "icache");
@@ -1548,7 +1557,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
15481557
SZ_256K - SZ_16K, 0x44000, "dcache");
15491558
if (ret)
15501559
goto err_memory;
1551-
} else {
1560+
} else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) {
15521561
/* HFI v1, has sptprac */
15531562
gmu->legacy = true;
15541563

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 69 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -252,6 +252,74 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
252252
a6xx_flush(gpu, ring);
253253
}
254254

255+
/* For a615 family (a615, a616, a618 and a619) */
256+
const struct adreno_reglist a615_hwcg[] = {
257+
{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
258+
{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
259+
{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
260+
{REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
261+
{REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
262+
{REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
263+
{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
264+
{REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
265+
{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
266+
{REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
267+
{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
268+
{REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
269+
{REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
270+
{REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
271+
{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
272+
{REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
273+
{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
274+
{REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
275+
{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
276+
{REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
277+
{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
278+
{REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
279+
{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
280+
{REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
281+
{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
282+
{REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
283+
{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
284+
{REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
285+
{REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
286+
{REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
287+
{REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
288+
{REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
289+
{REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
290+
{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
291+
{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
292+
{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
293+
{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
294+
{REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
295+
{REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
296+
{REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
297+
{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
298+
{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
299+
{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
300+
{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
301+
{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
302+
{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
303+
{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
304+
{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
305+
{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
306+
{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
307+
{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
308+
{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
309+
{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
310+
{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
311+
{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
312+
{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
313+
{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
314+
{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
315+
{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
316+
{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
317+
{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
318+
{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
319+
{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
320+
{},
321+
};
322+
255323
const struct adreno_reglist a630_hwcg[] = {
256324
{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
257325
{REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
@@ -555,7 +623,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
555623
gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
556624
}
557625

558-
/* For a615, a616, a618, A619, a630, a640 and a680 */
626+
/* For a615, a616, a618, a619, a630, a640 and a680 */
559627
static const u32 a6xx_protect[] = {
560628
A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
561629
A6XX_PROTECT_RDONLY(0x00501, 0x0005),

‎drivers/gpu/drm/msm/adreno/a6xx_hfi.c‎

Lines changed: 63 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -205,8 +205,8 @@ static int a6xx_hfi_get_fw_version(struct a6xx_gmu *gmu, u32 *version)
205205
{
206206
struct a6xx_hfi_msg_fw_version msg = { 0 };
207207

208-
/* Currently supporting version 1.1 */
209-
msg.supported_version = (1 << 28) | (1 << 16);
208+
/* Currently supporting version 1.10 */
209+
msg.supported_version = (1 << 28) | (1 << 19) | (1 << 17);
210210

211211
return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_FW_VERSION, &msg, sizeof(msg),
212212
version, sizeof(*version));
@@ -285,6 +285,65 @@ static void a618_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
285285
msg->cnoc_cmds_data[1][0] = 0x60000001;
286286
}
287287

288+
static void a619_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
289+
{
290+
msg->bw_level_num = 13;
291+
292+
msg->ddr_cmds_num = 3;
293+
msg->ddr_wait_bitmask = 0x0;
294+
295+
msg->ddr_cmds_addrs[0] = 0x50000;
296+
msg->ddr_cmds_addrs[1] = 0x50004;
297+
msg->ddr_cmds_addrs[2] = 0x50080;
298+
299+
msg->ddr_cmds_data[0][0] = 0x40000000;
300+
msg->ddr_cmds_data[0][1] = 0x40000000;
301+
msg->ddr_cmds_data[0][2] = 0x40000000;
302+
msg->ddr_cmds_data[1][0] = 0x6000030c;
303+
msg->ddr_cmds_data[1][1] = 0x600000db;
304+
msg->ddr_cmds_data[1][2] = 0x60000008;
305+
msg->ddr_cmds_data[2][0] = 0x60000618;
306+
msg->ddr_cmds_data[2][1] = 0x600001b6;
307+
msg->ddr_cmds_data[2][2] = 0x60000008;
308+
msg->ddr_cmds_data[3][0] = 0x60000925;
309+
msg->ddr_cmds_data[3][1] = 0x60000291;
310+
msg->ddr_cmds_data[3][2] = 0x60000008;
311+
msg->ddr_cmds_data[4][0] = 0x60000dc1;
312+
msg->ddr_cmds_data[4][1] = 0x600003dc;
313+
msg->ddr_cmds_data[4][2] = 0x60000008;
314+
msg->ddr_cmds_data[5][0] = 0x600010ad;
315+
msg->ddr_cmds_data[5][1] = 0x600004ae;
316+
msg->ddr_cmds_data[5][2] = 0x60000008;
317+
msg->ddr_cmds_data[6][0] = 0x600014c3;
318+
msg->ddr_cmds_data[6][1] = 0x600005d4;
319+
msg->ddr_cmds_data[6][2] = 0x60000008;
320+
msg->ddr_cmds_data[7][0] = 0x6000176a;
321+
msg->ddr_cmds_data[7][1] = 0x60000693;
322+
msg->ddr_cmds_data[7][2] = 0x60000008;
323+
msg->ddr_cmds_data[8][0] = 0x60001f01;
324+
msg->ddr_cmds_data[8][1] = 0x600008b5;
325+
msg->ddr_cmds_data[8][2] = 0x60000008;
326+
msg->ddr_cmds_data[9][0] = 0x60002940;
327+
msg->ddr_cmds_data[9][1] = 0x60000b95;
328+
msg->ddr_cmds_data[9][2] = 0x60000008;
329+
msg->ddr_cmds_data[10][0] = 0x60002f68;
330+
msg->ddr_cmds_data[10][1] = 0x60000d50;
331+
msg->ddr_cmds_data[10][2] = 0x60000008;
332+
msg->ddr_cmds_data[11][0] = 0x60003700;
333+
msg->ddr_cmds_data[11][1] = 0x60000f71;
334+
msg->ddr_cmds_data[11][2] = 0x60000008;
335+
msg->ddr_cmds_data[12][0] = 0x60003fce;
336+
msg->ddr_cmds_data[12][1] = 0x600011ea;
337+
msg->ddr_cmds_data[12][2] = 0x60000008;
338+
339+
msg->cnoc_cmds_num = 1;
340+
msg->cnoc_wait_bitmask = 0x0;
341+
342+
msg->cnoc_cmds_addrs[0] = 0x50054;
343+
344+
msg->cnoc_cmds_data[0][0] = 0x40000000;
345+
}
346+
288347
static void a640_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
289348
{
290349
/*
@@ -462,6 +521,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
462521

463522
if (adreno_is_a618(adreno_gpu))
464523
a618_build_bw_table(&msg);
524+
else if (adreno_is_a619(adreno_gpu))
525+
a619_build_bw_table(&msg);
465526
else if (adreno_is_a640_family(adreno_gpu))
466527
a640_build_bw_table(&msg);
467528
else if (adreno_is_a650(adreno_gpu))

‎drivers/gpu/drm/msm/adreno/adreno_device.c‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -264,6 +264,19 @@ static const struct adreno_info gpulist[] = {
264264
.gmem = SZ_512K,
265265
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
266266
.init = a6xx_gpu_init,
267+
}, {
268+
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
269+
.revn = 619,
270+
.name = "A619",
271+
.fw = {
272+
[ADRENO_FW_SQE] = "a630_sqe.fw",
273+
[ADRENO_FW_GMU] = "a619_gmu.bin",
274+
},
275+
.gmem = SZ_512K,
276+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
277+
.init = a6xx_gpu_init,
278+
.zapfw = "a615_zap.mdt",
279+
.hwcg = a615_hwcg,
267280
}, {
268281
.rev = ADRENO_REV(6, 3, 0, ANY_ID),
269282
.revn = 630,
@@ -355,6 +368,7 @@ MODULE_FIRMWARE("qcom/a530_zap.mdt");
355368
MODULE_FIRMWARE("qcom/a530_zap.b00");
356369
MODULE_FIRMWARE("qcom/a530_zap.b01");
357370
MODULE_FIRMWARE("qcom/a530_zap.b02");
371+
MODULE_FIRMWARE("qcom/a619_gmu.bin");
358372
MODULE_FIRMWARE("qcom/a630_sqe.fw");
359373
MODULE_FIRMWARE("qcom/a630_gmu.bin");
360374
MODULE_FIRMWARE("qcom/a630_zap.mbn");

‎drivers/gpu/drm/msm/adreno/adreno_gpu.h‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ struct adreno_reglist {
5757
u32 value;
5858
};
5959

60-
extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
60+
extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
6161

6262
struct adreno_info {
6363
struct adreno_rev rev;
@@ -242,6 +242,11 @@ static inline int adreno_is_a618(struct adreno_gpu *gpu)
242242
return gpu->revn == 618;
243243
}
244244

245+
static inline int adreno_is_a619(struct adreno_gpu *gpu)
246+
{
247+
return gpu->revn == 619;
248+
}
249+
245250
static inline int adreno_is_a630(struct adreno_gpu *gpu)
246251
{
247252
return gpu->revn == 630;
@@ -268,6 +273,12 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
268273
return gpu->revn == 660;
269274
}
270275

276+
/* check for a615, a616, a618, a619 or any derivatives */
277+
static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
278+
{
279+
return gpu->revn == 615 || gpu->revn == 616 || gpu->revn == 618 || gpu->revn == 619;
280+
}
281+
271282
static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
272283
{
273284
return adreno_is_a660(gpu) || adreno_is_7c3(gpu);

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