Skip to content

Commit acddfc2

Browse files
WeiyiLu-MediaTekbebarino
WeiyiLu-MediaTek
authored and
bebarino
committed
clk: mediatek: Add MT8183 clock support
Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <[email protected]> Tested-by: Nicolas Boichat <[email protected]> Reviewed-by: Nicolas Boichat <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
1 parent 23fe31d commit acddfc2

15 files changed

+2196
-0
lines changed

‎drivers/clk/mediatek/Kconfig‎

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -216,4 +216,79 @@ config COMMON_CLK_MT8173
216216
default ARCH_MEDIATEK
217217
---help---
218218
This driver supports MediaTek MT8173 clocks.
219+
220+
config COMMON_CLK_MT8183
221+
bool "Clock driver for MediaTek MT8183"
222+
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
223+
select COMMON_CLK_MEDIATEK
224+
default ARCH_MEDIATEK && ARM64
225+
help
226+
This driver supports MediaTek MT8183 basic clocks.
227+
228+
config COMMON_CLK_MT8183_AUDIOSYS
229+
bool "Clock driver for MediaTek MT8183 audiosys"
230+
depends on COMMON_CLK_MT8183
231+
help
232+
This driver supports MediaTek MT8183 audiosys clocks.
233+
234+
config COMMON_CLK_MT8183_CAMSYS
235+
bool "Clock driver for MediaTek MT8183 camsys"
236+
depends on COMMON_CLK_MT8183
237+
help
238+
This driver supports MediaTek MT8183 camsys clocks.
239+
240+
config COMMON_CLK_MT8183_IMGSYS
241+
bool "Clock driver for MediaTek MT8183 imgsys"
242+
depends on COMMON_CLK_MT8183
243+
help
244+
This driver supports MediaTek MT8183 imgsys clocks.
245+
246+
config COMMON_CLK_MT8183_IPU_CORE0
247+
bool "Clock driver for MediaTek MT8183 ipu_core0"
248+
depends on COMMON_CLK_MT8183
249+
help
250+
This driver supports MediaTek MT8183 ipu_core0 clocks.
251+
252+
config COMMON_CLK_MT8183_IPU_CORE1
253+
bool "Clock driver for MediaTek MT8183 ipu_core1"
254+
depends on COMMON_CLK_MT8183
255+
help
256+
This driver supports MediaTek MT8183 ipu_core1 clocks.
257+
258+
config COMMON_CLK_MT8183_IPU_ADL
259+
bool "Clock driver for MediaTek MT8183 ipu_adl"
260+
depends on COMMON_CLK_MT8183
261+
help
262+
This driver supports MediaTek MT8183 ipu_adl clocks.
263+
264+
config COMMON_CLK_MT8183_IPU_CONN
265+
bool "Clock driver for MediaTek MT8183 ipu_conn"
266+
depends on COMMON_CLK_MT8183
267+
help
268+
This driver supports MediaTek MT8183 ipu_conn clocks.
269+
270+
config COMMON_CLK_MT8183_MFGCFG
271+
bool "Clock driver for MediaTek MT8183 mfgcfg"
272+
depends on COMMON_CLK_MT8183
273+
help
274+
This driver supports MediaTek MT8183 mfgcfg clocks.
275+
276+
config COMMON_CLK_MT8183_MMSYS
277+
bool "Clock driver for MediaTek MT8183 mmsys"
278+
depends on COMMON_CLK_MT8183
279+
help
280+
This driver supports MediaTek MT8183 mmsys clocks.
281+
282+
config COMMON_CLK_MT8183_VDECSYS
283+
bool "Clock driver for MediaTek MT8183 vdecsys"
284+
depends on COMMON_CLK_MT8183
285+
help
286+
This driver supports MediaTek MT8183 vdecsys clocks.
287+
288+
config COMMON_CLK_MT8183_VENCSYS
289+
bool "Clock driver for MediaTek MT8183 vencsys"
290+
depends on COMMON_CLK_MT8183
291+
help
292+
This driver supports MediaTek MT8183 vencsys clocks.
293+
219294
endmenu

‎drivers/clk/mediatek/Makefile‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,3 +32,15 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
3232
obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
3333
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
3434
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
35+
obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
36+
obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o
37+
obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o
38+
obj-$(CONFIG_COMMON_CLK_MT8183_IMGSYS) += clk-mt8183-img.o
39+
obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE0) += clk-mt8183-ipu0.o
40+
obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE1) += clk-mt8183-ipu1.o
41+
obj-$(CONFIG_COMMON_CLK_MT8183_IPU_ADL) += clk-mt8183-ipu_adl.o
42+
obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CONN) += clk-mt8183-ipu_conn.o
43+
obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
44+
obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
45+
obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
46+
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o

‎drivers/clk/mediatek/clk-gate.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,4 +50,18 @@ struct clk *mtk_clk_register_gate(
5050
const struct clk_ops *ops,
5151
unsigned long flags);
5252

53+
#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
54+
_ops, _flags) { \
55+
.id = _id, \
56+
.name = _name, \
57+
.parent_name = _parent, \
58+
.regs = _regs, \
59+
.shift = _shift, \
60+
.ops = _ops, \
61+
.flags = _flags, \
62+
}
63+
64+
#define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
65+
GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
66+
5367
#endif /* __DRV_CLK_GATE_H */

‎drivers/clk/mediatek/clk-mt8183-audio.c‎

Lines changed: 105 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,105 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
//
3+
// Copyright (c) 2018 MediaTek Inc.
4+
// Author: Weiyi Lu <[email protected]>
5+
6+
#include <linux/clk-provider.h>
7+
#include <linux/of_platform.h>
8+
#include <linux/platform_device.h>
9+
10+
#include "clk-mtk.h"
11+
#include "clk-gate.h"
12+
13+
#include <dt-bindings/clock/mt8183-clk.h>
14+
15+
static const struct mtk_gate_regs audio0_cg_regs = {
16+
.set_ofs = 0x0,
17+
.clr_ofs = 0x0,
18+
.sta_ofs = 0x0,
19+
};
20+
21+
static const struct mtk_gate_regs audio1_cg_regs = {
22+
.set_ofs = 0x4,
23+
.clr_ofs = 0x4,
24+
.sta_ofs = 0x4,
25+
};
26+
27+
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
28+
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
29+
&mtk_clk_gate_ops_no_setclr)
30+
31+
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
32+
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
33+
&mtk_clk_gate_ops_no_setclr)
34+
35+
static const struct mtk_gate audio_clks[] = {
36+
/* AUDIO0 */
37+
GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",
38+
2),
39+
GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",
40+
8),
41+
GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",
42+
9),
43+
GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
44+
18),
45+
GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
46+
19),
47+
GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",
48+
20),
49+
GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",
50+
24),
51+
GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",
52+
25),
53+
GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",
54+
26),
55+
GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",
56+
27),
57+
/* AUDIO1 */
58+
GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",
59+
4),
60+
GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",
61+
5),
62+
GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",
63+
6),
64+
GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",
65+
7),
66+
GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
67+
20),
68+
};
69+
70+
static int clk_mt8183_audio_probe(struct platform_device *pdev)
71+
{
72+
struct clk_onecell_data *clk_data;
73+
int r;
74+
struct device_node *node = pdev->dev.of_node;
75+
76+
clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
77+
78+
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
79+
clk_data);
80+
81+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
82+
if (r)
83+
return r;
84+
85+
r = devm_of_platform_populate(&pdev->dev);
86+
if (r)
87+
of_clk_del_provider(node);
88+
89+
return r;
90+
}
91+
92+
static const struct of_device_id of_match_clk_mt8183_audio[] = {
93+
{ .compatible = "mediatek,mt8183-audiosys", },
94+
{}
95+
};
96+
97+
static struct platform_driver clk_mt8183_audio_drv = {
98+
.probe = clk_mt8183_audio_probe,
99+
.driver = {
100+
.name = "clk-mt8183-audio",
101+
.of_match_table = of_match_clk_mt8183_audio,
102+
},
103+
};
104+
105+
builtin_platform_driver(clk_mt8183_audio_drv);

‎drivers/clk/mediatek/clk-mt8183-cam.c‎

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
//
3+
// Copyright (c) 2018 MediaTek Inc.
4+
// Author: Weiyi Lu <[email protected]>
5+
6+
#include <linux/clk-provider.h>
7+
#include <linux/platform_device.h>
8+
9+
#include "clk-mtk.h"
10+
#include "clk-gate.h"
11+
12+
#include <dt-bindings/clock/mt8183-clk.h>
13+
14+
static const struct mtk_gate_regs cam_cg_regs = {
15+
.set_ofs = 0x4,
16+
.clr_ofs = 0x8,
17+
.sta_ofs = 0x0,
18+
};
19+
20+
#define GATE_CAM(_id, _name, _parent, _shift) \
21+
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
22+
&mtk_clk_gate_ops_setclr)
23+
24+
static const struct mtk_gate cam_clks[] = {
25+
GATE_CAM(CLK_CAM_LARB6, "cam_larb6", "cam_sel", 0),
26+
GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
27+
GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "cam_sel", 2),
28+
GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
29+
GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
30+
GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
31+
GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
32+
GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
33+
GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
34+
GATE_CAM(CLK_CAM_CCU, "cam_ccu", "cam_sel", 12),
35+
};
36+
37+
static int clk_mt8183_cam_probe(struct platform_device *pdev)
38+
{
39+
struct clk_onecell_data *clk_data;
40+
struct device_node *node = pdev->dev.of_node;
41+
42+
clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
43+
44+
mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
45+
clk_data);
46+
47+
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
48+
}
49+
50+
static const struct of_device_id of_match_clk_mt8183_cam[] = {
51+
{ .compatible = "mediatek,mt8183-camsys", },
52+
{}
53+
};
54+
55+
static struct platform_driver clk_mt8183_cam_drv = {
56+
.probe = clk_mt8183_cam_probe,
57+
.driver = {
58+
.name = "clk-mt8183-cam",
59+
.of_match_table = of_match_clk_mt8183_cam,
60+
},
61+
};
62+
63+
builtin_platform_driver(clk_mt8183_cam_drv);

‎drivers/clk/mediatek/clk-mt8183-img.c‎

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
//
3+
// Copyright (c) 2018 MediaTek Inc.
4+
// Author: Weiyi Lu <[email protected]>
5+
6+
#include <linux/clk-provider.h>
7+
#include <linux/platform_device.h>
8+
9+
#include "clk-mtk.h"
10+
#include "clk-gate.h"
11+
12+
#include <dt-bindings/clock/mt8183-clk.h>
13+
14+
static const struct mtk_gate_regs img_cg_regs = {
15+
.set_ofs = 0x4,
16+
.clr_ofs = 0x8,
17+
.sta_ofs = 0x0,
18+
};
19+
20+
#define GATE_IMG(_id, _name, _parent, _shift) \
21+
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
22+
&mtk_clk_gate_ops_setclr)
23+
24+
static const struct mtk_gate img_clks[] = {
25+
GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0),
26+
GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1),
27+
GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2),
28+
GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3),
29+
GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4),
30+
GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5),
31+
GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6),
32+
GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7),
33+
GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8),
34+
GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
35+
};
36+
37+
static int clk_mt8183_img_probe(struct platform_device *pdev)
38+
{
39+
struct clk_onecell_data *clk_data;
40+
struct device_node *node = pdev->dev.of_node;
41+
42+
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
43+
44+
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
45+
clk_data);
46+
47+
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
48+
}
49+
50+
static const struct of_device_id of_match_clk_mt8183_img[] = {
51+
{ .compatible = "mediatek,mt8183-imgsys", },
52+
{}
53+
};
54+
55+
static struct platform_driver clk_mt8183_img_drv = {
56+
.probe = clk_mt8183_img_probe,
57+
.driver = {
58+
.name = "clk-mt8183-img",
59+
.of_match_table = of_match_clk_mt8183_img,
60+
},
61+
};
62+
63+
builtin_platform_driver(clk_mt8183_img_drv);

0 commit comments

Comments
 (0)