@@ -244,132 +244,6 @@ static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
244244 generic_handle_domain_irq (icu_data [0 ].domain , hwirq );
245245}
246246
247- /* MMP (ARMv5) */
248- void __init icu_init_irq (void )
249- {
250- int irq ;
251-
252- max_icu_nr = 1 ;
253- mmp_icu_base = ioremap (0xd4282000 , 0x1000 );
254- icu_data [0 ].conf_enable = mmp_conf .conf_enable ;
255- icu_data [0 ].conf_disable = mmp_conf .conf_disable ;
256- icu_data [0 ].conf_mask = mmp_conf .conf_mask ;
257- icu_data [0 ].nr_irqs = 64 ;
258- icu_data [0 ].virq_base = 0 ;
259- icu_data [0 ].domain = irq_domain_add_legacy (NULL , 64 , 0 , 0 ,
260- & irq_domain_simple_ops ,
261- & icu_data [0 ]);
262- for (irq = 0 ; irq < 64 ; irq ++ ) {
263- icu_mask_irq (irq_get_irq_data (irq ));
264- irq_set_chip_and_handler (irq , & icu_irq_chip , handle_level_irq );
265- }
266- irq_set_default_host (icu_data [0 ].domain );
267- set_handle_irq (mmp_handle_irq );
268- }
269-
270- /* MMP2 (ARMv7) */
271- void __init mmp2_init_icu (void )
272- {
273- int irq , end ;
274-
275- max_icu_nr = 8 ;
276- mmp_icu_base = ioremap (0xd4282000 , 0x1000 );
277- icu_data [0 ].conf_enable = mmp2_conf .conf_enable ;
278- icu_data [0 ].conf_disable = mmp2_conf .conf_disable ;
279- icu_data [0 ].conf_mask = mmp2_conf .conf_mask ;
280- icu_data [0 ].nr_irqs = 64 ;
281- icu_data [0 ].virq_base = 0 ;
282- icu_data [0 ].domain = irq_domain_add_legacy (NULL , 64 , 0 , 0 ,
283- & irq_domain_simple_ops ,
284- & icu_data [0 ]);
285- icu_data [1 ].reg_status = mmp_icu_base + 0x150 ;
286- icu_data [1 ].reg_mask = mmp_icu_base + 0x168 ;
287- icu_data [1 ].clr_mfp_irq_base = icu_data [0 ].virq_base +
288- icu_data [0 ].nr_irqs ;
289- icu_data [1 ].clr_mfp_hwirq = 1 ; /* offset to IRQ_MMP2_PMIC_BASE */
290- icu_data [1 ].nr_irqs = 2 ;
291- icu_data [1 ].cascade_irq = 4 ;
292- icu_data [1 ].virq_base = icu_data [0 ].virq_base + icu_data [0 ].nr_irqs ;
293- icu_data [1 ].domain = irq_domain_add_legacy (NULL , icu_data [1 ].nr_irqs ,
294- icu_data [1 ].virq_base , 0 ,
295- & irq_domain_simple_ops ,
296- & icu_data [1 ]);
297- icu_data [2 ].reg_status = mmp_icu_base + 0x154 ;
298- icu_data [2 ].reg_mask = mmp_icu_base + 0x16c ;
299- icu_data [2 ].nr_irqs = 2 ;
300- icu_data [2 ].cascade_irq = 5 ;
301- icu_data [2 ].virq_base = icu_data [1 ].virq_base + icu_data [1 ].nr_irqs ;
302- icu_data [2 ].domain = irq_domain_add_legacy (NULL , icu_data [2 ].nr_irqs ,
303- icu_data [2 ].virq_base , 0 ,
304- & irq_domain_simple_ops ,
305- & icu_data [2 ]);
306- icu_data [3 ].reg_status = mmp_icu_base + 0x180 ;
307- icu_data [3 ].reg_mask = mmp_icu_base + 0x17c ;
308- icu_data [3 ].nr_irqs = 3 ;
309- icu_data [3 ].cascade_irq = 9 ;
310- icu_data [3 ].virq_base = icu_data [2 ].virq_base + icu_data [2 ].nr_irqs ;
311- icu_data [3 ].domain = irq_domain_add_legacy (NULL , icu_data [3 ].nr_irqs ,
312- icu_data [3 ].virq_base , 0 ,
313- & irq_domain_simple_ops ,
314- & icu_data [3 ]);
315- icu_data [4 ].reg_status = mmp_icu_base + 0x158 ;
316- icu_data [4 ].reg_mask = mmp_icu_base + 0x170 ;
317- icu_data [4 ].nr_irqs = 5 ;
318- icu_data [4 ].cascade_irq = 17 ;
319- icu_data [4 ].virq_base = icu_data [3 ].virq_base + icu_data [3 ].nr_irqs ;
320- icu_data [4 ].domain = irq_domain_add_legacy (NULL , icu_data [4 ].nr_irqs ,
321- icu_data [4 ].virq_base , 0 ,
322- & irq_domain_simple_ops ,
323- & icu_data [4 ]);
324- icu_data [5 ].reg_status = mmp_icu_base + 0x15c ;
325- icu_data [5 ].reg_mask = mmp_icu_base + 0x174 ;
326- icu_data [5 ].nr_irqs = 15 ;
327- icu_data [5 ].cascade_irq = 35 ;
328- icu_data [5 ].virq_base = icu_data [4 ].virq_base + icu_data [4 ].nr_irqs ;
329- icu_data [5 ].domain = irq_domain_add_legacy (NULL , icu_data [5 ].nr_irqs ,
330- icu_data [5 ].virq_base , 0 ,
331- & irq_domain_simple_ops ,
332- & icu_data [5 ]);
333- icu_data [6 ].reg_status = mmp_icu_base + 0x160 ;
334- icu_data [6 ].reg_mask = mmp_icu_base + 0x178 ;
335- icu_data [6 ].nr_irqs = 2 ;
336- icu_data [6 ].cascade_irq = 51 ;
337- icu_data [6 ].virq_base = icu_data [5 ].virq_base + icu_data [5 ].nr_irqs ;
338- icu_data [6 ].domain = irq_domain_add_legacy (NULL , icu_data [6 ].nr_irqs ,
339- icu_data [6 ].virq_base , 0 ,
340- & irq_domain_simple_ops ,
341- & icu_data [6 ]);
342- icu_data [7 ].reg_status = mmp_icu_base + 0x188 ;
343- icu_data [7 ].reg_mask = mmp_icu_base + 0x184 ;
344- icu_data [7 ].nr_irqs = 2 ;
345- icu_data [7 ].cascade_irq = 55 ;
346- icu_data [7 ].virq_base = icu_data [6 ].virq_base + icu_data [6 ].nr_irqs ;
347- icu_data [7 ].domain = irq_domain_add_legacy (NULL , icu_data [7 ].nr_irqs ,
348- icu_data [7 ].virq_base , 0 ,
349- & irq_domain_simple_ops ,
350- & icu_data [7 ]);
351- end = icu_data [7 ].virq_base + icu_data [7 ].nr_irqs ;
352- for (irq = 0 ; irq < end ; irq ++ ) {
353- icu_mask_irq (irq_get_irq_data (irq ));
354- if (irq == icu_data [1 ].cascade_irq ||
355- irq == icu_data [2 ].cascade_irq ||
356- irq == icu_data [3 ].cascade_irq ||
357- irq == icu_data [4 ].cascade_irq ||
358- irq == icu_data [5 ].cascade_irq ||
359- irq == icu_data [6 ].cascade_irq ||
360- irq == icu_data [7 ].cascade_irq ) {
361- irq_set_chip (irq , & icu_irq_chip );
362- irq_set_chained_handler (irq , icu_mux_irq_demux );
363- } else {
364- irq_set_chip_and_handler (irq , & icu_irq_chip ,
365- handle_level_irq );
366- }
367- }
368- irq_set_default_host (icu_data [0 ].domain );
369- set_handle_irq (mmp2_handle_irq );
370- }
371-
372- #ifdef CONFIG_OF
373247static int __init mmp_init_bases (struct device_node * node )
374248{
375249 int ret , nr_irqs , irq , i = 0 ;
@@ -548,4 +422,3 @@ static int __init mmp2_mux_of_init(struct device_node *node,
548422 return - EINVAL ;
549423}
550424IRQCHIP_DECLARE (mmp2_mux_intc , "mrvl,mmp2-mux-intc" , mmp2_mux_of_init );
551- #endif
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