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2 parents 26b0833 + 84a6fcb commit 9f3a628Copy full SHA for 9f3a628
arch/mips/bcm47xx/prom.c
@@ -141,6 +141,14 @@ static __init void prom_init_mem(void)
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break;
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}
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+ /* Ignoring the last page when ddr size is 128M. Cached
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+ * accesses to last page is causing the processor to prefetch
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+ * using address above 128M stepping out of the ddr address
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+ * space.
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+ */
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+ if (mem == 0x8000000)
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+ mem -= 0x1000;
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+
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add_memory_region(0, mem, BOOT_MEM_RAM);
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arch/mips/mm/highmem.c
@@ -1,5 +1,6 @@
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#include <linux/module.h>
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#include <linux/highmem.h>
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+#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/fixmap.h>
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#include <asm/tlbflush.h>
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