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viviendavem330
vivien
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net: dsa: mv88e6xxx: add RMU disable op
The RMU mode bits moved a lot within the Global Control 2 register of the Marvell switch families. Add an .rmu_disable op to support at least 3 known alternatives. Signed-off-by: Vivien Didelot <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/dsa/mv88e6xxx/chip.c‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1069,6 +1069,14 @@ static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
10691069
return 0;
10701070
}
10711071

1072+
static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1073+
{
1074+
if (chip->info->ops->rmu_disable)
1075+
return chip->info->ops->rmu_disable(chip);
1076+
1077+
return 0;
1078+
}
1079+
10721080
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
10731081
{
10741082
if (chip->info->ops->pot_clear)
@@ -2263,6 +2271,10 @@ static int mv88e6xxx_setup(struct dsa_switch *ds)
22632271
if (err)
22642272
goto unlock;
22652273

2274+
err = mv88e6xxx_rmu_setup(chip);
2275+
if (err)
2276+
goto unlock;
2277+
22662278
err = mv88e6xxx_rsvd2cpu_setup(chip);
22672279
if (err)
22682280
goto unlock;
@@ -2530,6 +2542,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
25302542
.ppu_enable = mv88e6185_g1_ppu_enable,
25312543
.ppu_disable = mv88e6185_g1_ppu_disable,
25322544
.reset = mv88e6185_g1_reset,
2545+
.rmu_disable = mv88e6085_g1_rmu_disable,
25332546
.vtu_getnext = mv88e6352_g1_vtu_getnext,
25342547
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
25352548
.serdes_power = mv88e6341_serdes_power,
@@ -2588,6 +2601,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
25882601
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
25892602
.pot_clear = mv88e6xxx_g2_pot_clear,
25902603
.reset = mv88e6352_g1_reset,
2604+
.rmu_disable = mv88e6085_g1_rmu_disable,
25912605
.vtu_getnext = mv88e6352_g1_vtu_getnext,
25922606
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
25932607
};
@@ -2815,6 +2829,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
28152829
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
28162830
.pot_clear = mv88e6xxx_g2_pot_clear,
28172831
.reset = mv88e6352_g1_reset,
2832+
.rmu_disable = mv88e6352_g1_rmu_disable,
28182833
.vtu_getnext = mv88e6352_g1_vtu_getnext,
28192834
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
28202835
.serdes_power = mv88e6352_serdes_power,
@@ -2888,6 +2903,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
28882903
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
28892904
.pot_clear = mv88e6xxx_g2_pot_clear,
28902905
.reset = mv88e6352_g1_reset,
2906+
.rmu_disable = mv88e6352_g1_rmu_disable,
28912907
.vtu_getnext = mv88e6352_g1_vtu_getnext,
28922908
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
28932909
.serdes_power = mv88e6352_serdes_power,
@@ -2953,6 +2969,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
29532969
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
29542970
.pot_clear = mv88e6xxx_g2_pot_clear,
29552971
.reset = mv88e6352_g1_reset,
2972+
.rmu_disable = mv88e6390_g1_rmu_disable,
29562973
.vtu_getnext = mv88e6390_g1_vtu_getnext,
29572974
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
29582975
.serdes_power = mv88e6390_serdes_power,
@@ -2989,6 +3006,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
29893006
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
29903007
.pot_clear = mv88e6xxx_g2_pot_clear,
29913008
.reset = mv88e6352_g1_reset,
3009+
.rmu_disable = mv88e6390_g1_rmu_disable,
29923010
.vtu_getnext = mv88e6390_g1_vtu_getnext,
29933011
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
29943012
.serdes_power = mv88e6390_serdes_power,
@@ -3025,6 +3043,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
30253043
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
30263044
.pot_clear = mv88e6xxx_g2_pot_clear,
30273045
.reset = mv88e6352_g1_reset,
3046+
.rmu_disable = mv88e6390_g1_rmu_disable,
30283047
.vtu_getnext = mv88e6390_g1_vtu_getnext,
30293048
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
30303049
.serdes_power = mv88e6390_serdes_power,
@@ -3062,6 +3081,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
30623081
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
30633082
.pot_clear = mv88e6xxx_g2_pot_clear,
30643083
.reset = mv88e6352_g1_reset,
3084+
.rmu_disable = mv88e6352_g1_rmu_disable,
30653085
.vtu_getnext = mv88e6352_g1_vtu_getnext,
30663086
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
30673087
.serdes_power = mv88e6352_serdes_power,
@@ -3100,6 +3120,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
31003120
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
31013121
.pot_clear = mv88e6xxx_g2_pot_clear,
31023122
.reset = mv88e6352_g1_reset,
3123+
.rmu_disable = mv88e6390_g1_rmu_disable,
31033124
.vtu_getnext = mv88e6390_g1_vtu_getnext,
31043125
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
31053126
.serdes_power = mv88e6390_serdes_power,
@@ -3316,6 +3337,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
33163337
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
33173338
.pot_clear = mv88e6xxx_g2_pot_clear,
33183339
.reset = mv88e6352_g1_reset,
3340+
.rmu_disable = mv88e6352_g1_rmu_disable,
33193341
.vtu_getnext = mv88e6352_g1_vtu_getnext,
33203342
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
33213343
.serdes_power = mv88e6352_serdes_power,
@@ -3359,6 +3381,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
33593381
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
33603382
.pot_clear = mv88e6xxx_g2_pot_clear,
33613383
.reset = mv88e6352_g1_reset,
3384+
.rmu_disable = mv88e6390_g1_rmu_disable,
33623385
.vtu_getnext = mv88e6390_g1_vtu_getnext,
33633386
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
33643387
.serdes_power = mv88e6390_serdes_power,
@@ -3399,6 +3422,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
33993422
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
34003423
.pot_clear = mv88e6xxx_g2_pot_clear,
34013424
.reset = mv88e6352_g1_reset,
3425+
.rmu_disable = mv88e6390_g1_rmu_disable,
34023426
.vtu_getnext = mv88e6390_g1_vtu_getnext,
34033427
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
34043428
.serdes_power = mv88e6390_serdes_power,

‎drivers/net/dsa/mv88e6xxx/chip.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -432,6 +432,9 @@ struct mv88e6xxx_ops {
432432

433433
/* Interface to the AVB/PTP registers */
434434
const struct mv88e6xxx_avb_ops *avb_ops;
435+
436+
/* Remote Management Unit operations */
437+
int (*rmu_disable)(struct mv88e6xxx_chip *chip);
435438
};
436439

437440
struct mv88e6xxx_irq_ops {

‎drivers/net/dsa/mv88e6xxx/global1.c‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -373,6 +373,24 @@ int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
373373
return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
374374
}
375375

376+
int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
377+
{
378+
return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
379+
MV88E6085_G1_CTL2_RM_ENABLE, 0);
380+
}
381+
382+
int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
383+
{
384+
return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
385+
MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
386+
}
387+
388+
int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
389+
{
390+
return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
391+
MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
392+
}
393+
376394
int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
377395
{
378396
u16 val;

‎drivers/net/dsa/mv88e6xxx/global1.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,22 @@
207207
#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
208208
#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
209209
#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
210+
#define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000
211+
#define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000
212+
#define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000
213+
#define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000
214+
#define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000
215+
#define MV88E6085_G1_CTL2_DA_CHECK 0x4000
216+
#define MV88E6085_G1_CTL2_P10RM 0x2000
217+
#define MV88E6085_G1_CTL2_RM_ENABLE 0x1000
218+
#define MV88E6352_G1_CTL2_DA_CHECK 0x0800
219+
#define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700
220+
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000
221+
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100
222+
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200
223+
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300
224+
#define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600
225+
#define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700
210226
#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f
211227

212228
/* Offset 0x1D: Stats Operation Register */
@@ -257,6 +273,10 @@ int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
257273

258274
int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
259275

276+
int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
277+
int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
278+
int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
279+
260280
int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
261281

262282
int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);

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