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gve: Add basic driver framework for Compute Engine Virtual NIC
Add a driver framework for the Compute Engine Virtual NIC that will be available in the future. At this point the only functionality is loading the driver. Signed-off-by: Catherine Sullivan <[email protected]> Signed-off-by: Sagi Shahar <[email protected]> Signed-off-by: Jon Olson <[email protected]> Acked-by: Willem de Bruijn <[email protected]> Reviewed-by: Luigi Rizzo <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎Documentation/networking/device_drivers/google/gve.rst‎

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.. SPDX-License-Identifier: GPL-2.0+
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==============================================================
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Linux kernel driver for Compute Engine Virtual Ethernet (gve):
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==============================================================
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Supported Hardware
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===================
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The GVE driver binds to a single PCI device id used by the virtual
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Ethernet device found in some Compute Engine VMs.
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+--------------+----------+---------+
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|Field | Value | Comments|
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+==============+==========+=========+
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|Vendor ID | `0x1AE0` | Google |
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+--------------+----------+---------+
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|Device ID | `0x0042` | |
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+--------------+----------+---------+
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|Sub-vendor ID | `0x1AE0` | Google |
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+--------------+----------+---------+
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|Sub-device ID | `0x0058` | |
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+--------------+----------+---------+
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|Revision ID | `0x0` | |
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+--------------+----------+---------+
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|Device Class | `0x200` | Ethernet|
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+--------------+----------+---------+
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PCI Bars
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========
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The gVNIC PCI device exposes three 32-bit memory BARS:
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- Bar0 - Device configuration and status registers.
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- Bar1 - MSI-X vector table
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- Bar2 - IRQ, RX and TX doorbells
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Device Interactions
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===================
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The driver interacts with the device in the following ways:
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- Registers
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- A block of MMIO registers
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- See gve_register.h for more detail
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- Admin Queue
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- See description below
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- Interrupts
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- See supported interrupts below
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Registers
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---------
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All registers are MMIO and big endian.
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The registers are used for initializing and configuring the device as well as
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querying device status in response to management interrupts.
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Admin Queue (AQ)
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----------------
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The Admin Queue is a PAGE_SIZE memory block, treated as an array of AQ
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commands, used by the driver to issue commands to the device and set up
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resources.The driver and the device maintain a count of how many commands
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have been submitted and executed. To issue AQ commands, the driver must do
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the following (with proper locking):
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1) Copy new commands into next available slots in the AQ array
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2) Increment its counter by he number of new commands
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3) Write the counter into the GVE_ADMIN_QUEUE_DOORBELL register
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4) Poll the ADMIN_QUEUE_EVENT_COUNTER register until it equals
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the value written to the doorbell, or until a timeout.
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The device will update the status field in each AQ command reported as
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executed through the ADMIN_QUEUE_EVENT_COUNTER register.
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Interrupts
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----------
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The following interrupts are supported by the driver:
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Management Interrupt
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~~~~~~~~~~~~~~~~~~~~
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The management interrupt is used by the device to tell the driver to
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look at the GVE_DEVICE_STATUS register.
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Notification Block Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The notification block interrupts are used to tell the driver to poll
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the queues associated with that interrupt.

‎Documentation/networking/device_drivers/index.rst‎

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intel/i40e
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intel/iavf
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intel/ice
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google/gve
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mellanox/mlx5
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.. only:: subproject

‎MAINTAINERS‎

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S: Maintained
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F: drivers/input/touchscreen/goodix.c
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GOOGLE ETHERNET DRIVERS
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M: Catherine Sullivan <[email protected]>
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R: Sagi Shahar <[email protected]>
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R: Jon Olson <[email protected]>
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L: [email protected]
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S: Supported
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F: Documentation/networking/device_drivers/google/gve.txt
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F: drivers/net/ethernet/google
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GPD POCKET FAN DRIVER
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M: Hans de Goede <[email protected]>
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L: [email protected]

‎drivers/net/ethernet/Kconfig‎

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source "drivers/net/ethernet/faraday/Kconfig"
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source "drivers/net/ethernet/freescale/Kconfig"
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source "drivers/net/ethernet/fujitsu/Kconfig"
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source "drivers/net/ethernet/google/Kconfig"
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source "drivers/net/ethernet/hisilicon/Kconfig"
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source "drivers/net/ethernet/hp/Kconfig"
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source "drivers/net/ethernet/huawei/Kconfig"

‎drivers/net/ethernet/Makefile‎

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obj-$(CONFIG_NET_VENDOR_FARADAY) += faraday/
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obj-$(CONFIG_NET_VENDOR_FREESCALE) += freescale/
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obj-$(CONFIG_NET_VENDOR_FUJITSU) += fujitsu/
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obj-$(CONFIG_NET_VENDOR_GOOGLE) += google/
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obj-$(CONFIG_NET_VENDOR_HISILICON) += hisilicon/
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obj-$(CONFIG_NET_VENDOR_HP) += hp/
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obj-$(CONFIG_NET_VENDOR_HUAWEI) += huawei/

‎drivers/net/ethernet/google/Kconfig‎

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#
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# Google network device configuration
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#
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config NET_VENDOR_GOOGLE
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bool "Google Devices"
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default y
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help
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If you have a network (Ethernet) device belonging to this class, say Y.
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Note that the answer to this question doesn't directly affect the
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kernel: saying N will just cause the configurator to skip all
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the questions about Google devices. If you say Y, you will be asked
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for your specific device in the following questions.
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if NET_VENDOR_GOOGLE
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config GVE
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tristate "Google Virtual NIC (gVNIC) support"
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depends on PCI_MSI
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help
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This driver supports Google Virtual NIC (gVNIC)"
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To compile this driver as a module, choose M here.
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The module will be called gve.
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endif #NET_VENDOR_GOOGLE

‎drivers/net/ethernet/google/Makefile‎

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#
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# Makefile for the Google network device drivers.
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#
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obj-$(CONFIG_GVE) += gve/

‎drivers/net/ethernet/google/gve/Makefile‎

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# Makefile for the Google virtual Ethernet (gve) driver
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obj-$(CONFIG_GVE) += gve.o
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gve-objs := gve_main.o gve_adminq.o

‎drivers/net/ethernet/google/gve/gve.h‎

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/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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* Google virtual Ethernet (gve) driver
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*
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* Copyright (C) 2015-2019 Google, Inc.
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*/
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#ifndef _GVE_H_
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#define _GVE_H_
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#include <linux/dma-mapping.h>
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#include <linux/netdevice.h>
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#include <linux/pci.h>
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#ifndef PCI_VENDOR_ID_GOOGLE
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#define PCI_VENDOR_ID_GOOGLE 0x1ae0
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#endif
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#define PCI_DEV_ID_GVNIC 0x0042
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#define GVE_REGISTER_BAR 0
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#define GVE_DOORBELL_BAR 2
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/* 1 for management */
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#define GVE_MIN_MSIX 3
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struct gve_notify_block {
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__be32 irq_db_index; /* idx into Bar2 - set by device, must be 1st */
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char name[IFNAMSIZ + 16]; /* name registered with the kernel */
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struct napi_struct napi; /* kernel napi struct for this block */
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struct gve_priv *priv;
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} ____cacheline_aligned;
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struct gve_priv {
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struct net_device *dev;
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struct gve_notify_block *ntfy_blocks; /* array of num_ntfy_blks */
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dma_addr_t ntfy_block_bus;
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struct msix_entry *msix_vectors; /* array of num_ntfy_blks + 1 */
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char mgmt_msix_name[IFNAMSIZ + 16];
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u32 mgmt_msix_idx;
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__be32 *counter_array; /* array of num_event_counters */
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dma_addr_t counter_array_bus;
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u16 num_event_counters;
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u32 num_ntfy_blks; /* spilt between TX and RX so must be even */
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struct gve_registers __iomem *reg_bar0; /* see gve_register.h */
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__be32 __iomem *db_bar2; /* "array" of doorbells */
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u32 msg_enable; /* level for netif* netdev print macros */
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struct pci_dev *pdev;
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/* Admin queue - see gve_adminq.h*/
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union gve_adminq_command *adminq;
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dma_addr_t adminq_bus_addr;
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u32 adminq_mask; /* masks prod_cnt to adminq size */
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u32 adminq_prod_cnt; /* free-running count of AQ cmds executed */
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unsigned long state_flags;
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};
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enum gve_state_flags {
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GVE_PRIV_FLAGS_ADMIN_QUEUE_OK = BIT(1),
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GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK = BIT(2),
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GVE_PRIV_FLAGS_DEVICE_RINGS_OK = BIT(3),
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GVE_PRIV_FLAGS_NAPI_ENABLED = BIT(4),
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};
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static inline bool gve_get_admin_queue_ok(struct gve_priv *priv)
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{
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return test_bit(GVE_PRIV_FLAGS_ADMIN_QUEUE_OK, &priv->state_flags);
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}
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static inline void gve_set_admin_queue_ok(struct gve_priv *priv)
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{
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set_bit(GVE_PRIV_FLAGS_ADMIN_QUEUE_OK, &priv->state_flags);
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}
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static inline void gve_clear_admin_queue_ok(struct gve_priv *priv)
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{
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clear_bit(GVE_PRIV_FLAGS_ADMIN_QUEUE_OK, &priv->state_flags);
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}
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static inline bool gve_get_device_resources_ok(struct gve_priv *priv)
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{
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return test_bit(GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK, &priv->state_flags);
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}
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static inline void gve_set_device_resources_ok(struct gve_priv *priv)
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{
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set_bit(GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK, &priv->state_flags);
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}
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static inline void gve_clear_device_resources_ok(struct gve_priv *priv)
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{
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clear_bit(GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK, &priv->state_flags);
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}
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static inline bool gve_get_device_rings_ok(struct gve_priv *priv)
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{
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return test_bit(GVE_PRIV_FLAGS_DEVICE_RINGS_OK, &priv->state_flags);
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}
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static inline void gve_set_device_rings_ok(struct gve_priv *priv)
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{
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set_bit(GVE_PRIV_FLAGS_DEVICE_RINGS_OK, &priv->state_flags);
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}
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static inline void gve_clear_device_rings_ok(struct gve_priv *priv)
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{
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clear_bit(GVE_PRIV_FLAGS_DEVICE_RINGS_OK, &priv->state_flags);
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}
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static inline bool gve_get_napi_enabled(struct gve_priv *priv)
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{
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return test_bit(GVE_PRIV_FLAGS_NAPI_ENABLED, &priv->state_flags);
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}
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static inline void gve_set_napi_enabled(struct gve_priv *priv)
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{
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set_bit(GVE_PRIV_FLAGS_NAPI_ENABLED, &priv->state_flags);
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}
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static inline void gve_clear_napi_enabled(struct gve_priv *priv)
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{
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clear_bit(GVE_PRIV_FLAGS_NAPI_ENABLED, &priv->state_flags);
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}
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/* Returns the address of the ntfy_blocks irq doorbell
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*/
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static inline __be32 __iomem *gve_irq_doorbell(struct gve_priv *priv,
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struct gve_notify_block *block)
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{
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return &priv->db_bar2[be32_to_cpu(block->irq_db_index)];
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}
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#endif /* _GVE_H_ */

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