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net: phy: updated the initialization routine for LAN87xx
The new initialization sequence is the improvement to the existing init routine. Init routine does soft reset, run init script and set Hw_init. Added the new access_smi_poll_timeout() for polling smi bank write. Signed-off-by: Prasanna Vengateshan <[email protected]> Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/phy/microchip_t1.c‎

Lines changed: 175 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939
#define PHYACC_ATTR_MODE_READ 0
4040
#define PHYACC_ATTR_MODE_WRITE 1
4141
#define PHYACC_ATTR_MODE_MODIFY 2
42+
#define PHYACC_ATTR_MODE_POLL 3
4243

4344
#define PHYACC_ATTR_BANK_SMI 0
4445
#define PHYACC_ATTR_BANK_MISC 1
@@ -52,6 +53,28 @@
5253
#define LAN87XX_CABLE_TEST_OPEN 1
5354
#define LAN87XX_CABLE_TEST_SAME_SHORT 2
5455

56+
/* T1 Registers */
57+
#define T1_AFE_PORT_CFG1_REG 0x0B
58+
#define T1_POWER_DOWN_CONTROL_REG 0x1A
59+
#define T1_SLV_FD_MULT_CFG_REG 0x18
60+
#define T1_CDR_CFG_PRE_LOCK_REG 0x05
61+
#define T1_CDR_CFG_POST_LOCK_REG 0x06
62+
#define T1_LCK_STG2_MUFACT_CFG_REG 0x1A
63+
#define T1_LCK_STG3_MUFACT_CFG_REG 0x1B
64+
#define T1_POST_LCK_MUFACT_CFG_REG 0x1C
65+
#define T1_TX_RX_FIFO_CFG_REG 0x02
66+
#define T1_TX_LPF_FIR_CFG_REG 0x55
67+
#define T1_SQI_CONFIG_REG 0x2E
68+
#define T1_MDIO_CONTROL2_REG 0x10
69+
#define T1_INTERRUPT_SOURCE_REG 0x18
70+
#define T1_INTERRUPT2_SOURCE_REG 0x08
71+
#define T1_EQ_FD_STG1_FRZ_CFG 0x69
72+
#define T1_EQ_FD_STG2_FRZ_CFG 0x6A
73+
#define T1_EQ_FD_STG3_FRZ_CFG 0x6B
74+
#define T1_EQ_FD_STG4_FRZ_CFG 0x6C
75+
#define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D
76+
#define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E
77+
5578
#define DRIVER_AUTHOR "Nisar Sayed <[email protected]>"
5679
#define DRIVER_DESC "Microchip LAN87XX T1 PHY driver"
5780

@@ -119,6 +142,15 @@ static int access_ereg_modify_changed(struct phy_device *phydev,
119142
return rc;
120143
}
121144

145+
static int access_smi_poll_timeout(struct phy_device *phydev,
146+
u8 offset, u16 mask, u16 clr)
147+
{
148+
int val;
149+
150+
return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr,
151+
150, 30000, true);
152+
}
153+
122154
static int lan87xx_config_rgmii_delay(struct phy_device *phydev)
123155
{
124156
int rc;
@@ -159,58 +191,159 @@ static int lan87xx_config_rgmii_delay(struct phy_device *phydev)
159191
static int lan87xx_phy_init(struct phy_device *phydev)
160192
{
161193
static const struct access_ereg_val init[] = {
162-
/* TX Amplitude = 5 */
163-
{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_AFE, 0x0B,
164-
0x000A, 0x001E},
165-
/* Clear SMI interrupts */
166-
{PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 0x18,
167-
0, 0},
168-
/* Clear MISC interrupts */
169-
{PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC, 0x08,
170-
0, 0},
171-
/* Turn on TC10 Ring Oscillator (ROSC) */
172-
{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_MISC, 0x20,
173-
0x0020, 0x0020},
174-
/* WUR Detect Length to 1.2uS, LPC Detect Length to 1.09uS */
175-
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_PCS, 0x20,
176-
0x283C, 0},
177-
/* Wake_In Debounce Length to 39uS, Wake_Out Length to 79uS */
178-
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x21,
179-
0x274F, 0},
180-
/* Enable Auto Wake Forward to Wake_Out, ROSC on, Sleep,
181-
* and Wake_In to wake PHY
182-
*/
183-
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x20,
184-
0x80A7, 0},
185-
/* Enable WUP Auto Fwd, Enable Wake on MDI, Wakeup Debouncer
186-
* to 128 uS
187-
*/
188-
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x24,
189-
0xF110, 0},
190-
/* Enable HW Init */
191-
{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_SMI, 0x1A,
192-
0x0100, 0x0100},
194+
/* TXPD/TXAMP6 Configs */
195+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
196+
T1_AFE_PORT_CFG1_REG, 0x002D, 0 },
197+
/* HW_Init Hi and Force_ED */
198+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
199+
T1_POWER_DOWN_CONTROL_REG, 0x0308, 0 },
200+
/* Equalizer Full Duplex Freeze - T1 Slave */
201+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
202+
T1_EQ_FD_STG1_FRZ_CFG, 0x0002, 0 },
203+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
204+
T1_EQ_FD_STG2_FRZ_CFG, 0x0002, 0 },
205+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
206+
T1_EQ_FD_STG3_FRZ_CFG, 0x0002, 0 },
207+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
208+
T1_EQ_FD_STG4_FRZ_CFG, 0x0002, 0 },
209+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
210+
T1_EQ_WT_FD_LCK_FRZ_CFG, 0x0002, 0 },
211+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
212+
T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002, 0 },
213+
/* Slave Full Duplex Multi Configs */
214+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
215+
T1_SLV_FD_MULT_CFG_REG, 0x0D53, 0 },
216+
/* CDR Pre and Post Lock Configs */
217+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
218+
T1_CDR_CFG_PRE_LOCK_REG, 0x0AB2, 0 },
219+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
220+
T1_CDR_CFG_POST_LOCK_REG, 0x0AB3, 0 },
221+
/* Lock Stage 2-3 Multi Factor Config */
222+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
223+
T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA, 0 },
224+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
225+
T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB, 0 },
226+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
227+
T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB, 0 },
228+
/* Pointer delay */
229+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
230+
T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 },
231+
/* Tx iir edits */
232+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
233+
T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
234+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
235+
T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 },
236+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
237+
T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 },
238+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
239+
T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 },
240+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
241+
T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 },
242+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
243+
T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 },
244+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
245+
T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 },
246+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
247+
T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 },
248+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
249+
T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 },
250+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
251+
T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 },
252+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
253+
T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 },
254+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
255+
T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 },
256+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
257+
T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 },
258+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
259+
T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 },
260+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
261+
T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 },
262+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
263+
T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 },
264+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
265+
T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 },
266+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
267+
T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 },
268+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
269+
T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 },
270+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
271+
T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 },
272+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
273+
T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 },
274+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
275+
T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 },
276+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
277+
T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 },
278+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
279+
T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 },
280+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
281+
T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 },
282+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
283+
T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 },
284+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
285+
T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 },
286+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
287+
T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 },
288+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
289+
T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 },
290+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
291+
T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 },
292+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
293+
T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 },
294+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
295+
T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 },
296+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
297+
T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 },
298+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
299+
T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 },
300+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
301+
T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 },
302+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
303+
T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
304+
/* SQI enable */
305+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
306+
T1_SQI_CONFIG_REG, 0x9572, 0 },
307+
/* Flag LPS and WUR as idle errors */
308+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
309+
T1_MDIO_CONTROL2_REG, 0x0014, 0 },
310+
/* HW_Init toggle, undo force ED, TXPD off */
311+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
312+
T1_POWER_DOWN_CONTROL_REG, 0x0200, 0 },
313+
/* Reset PCS to trigger hardware initialization */
314+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
315+
T1_MDIO_CONTROL2_REG, 0x0094, 0 },
316+
/* Poll till Hardware is initialized */
317+
{ PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI,
318+
T1_MDIO_CONTROL2_REG, 0x0080, 0 },
319+
/* Tx AMP - 0x06 */
320+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
321+
T1_AFE_PORT_CFG1_REG, 0x000C, 0 },
322+
/* Read INTERRUPT_SOURCE Register */
323+
{ PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
324+
T1_INTERRUPT_SOURCE_REG, 0, 0 },
325+
/* Read INTERRUPT_SOURCE Register */
326+
{ PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC,
327+
T1_INTERRUPT2_SOURCE_REG, 0, 0 },
328+
/* HW_Init Hi */
329+
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
330+
T1_POWER_DOWN_CONTROL_REG, 0x0300, 0 },
193331
};
194332
int rc, i;
195333

196-
/* Start manual initialization procedures in Managed Mode */
197-
rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
198-
0x1a, 0x0000, 0x0100);
199-
if (rc < 0)
200-
return rc;
201-
202334
/* phy Soft reset */
203335
rc = genphy_soft_reset(phydev);
204336
if (rc < 0)
205337
return rc;
206338

207339
/* PHY Initialization */
208340
for (i = 0; i < ARRAY_SIZE(init); i++) {
209-
if (init[i].mode == PHYACC_ATTR_MODE_MODIFY) {
210-
rc = access_ereg_modify_changed(phydev, init[i].bank,
211-
init[i].offset,
212-
init[i].val,
213-
init[i].mask);
341+
if (init[i].mode == PHYACC_ATTR_MODE_POLL &&
342+
init[i].bank == PHYACC_ATTR_BANK_SMI) {
343+
rc = access_smi_poll_timeout(phydev,
344+
init[i].offset,
345+
init[i].val,
346+
init[i].mask);
214347
} else {
215348
rc = access_ereg(phydev, init[i].mode, init[i].bank,
216349
init[i].offset, init[i].val);

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