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yghannamKAGA-KOKO
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x86/mce: Init some CPU features early
When the MCA banks in __mcheck_cpu_init_generic() are polled for leftover errors logged during boot or from the previous boot, its required to have CPU features detected sufficiently so that the reading out and handling of those early errors is done correctly. If those features are not available, the decoding may miss some information and get incomplete errors logged. For example, on SMCA systems the MCA_IPID and MCA_SYND registers are not logged and MCA_ADDR is not masked appropriately. To cure that, do a subset of the basic feature detection early while the rest happens in its usual place in __mcheck_cpu_init_vendor(). Signed-off-by: Yazen Ghannam <[email protected]> Cc: Tony Luck <[email protected]> Cc: linux-edac <[email protected]> Cc: x86-ml <[email protected]> Link: http://lkml.kernel.org/r/[email protected] [ Massage commit message and simplify. ] Signed-off-by: Borislav Petkov <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]>
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  • arch/x86/kernel/cpu/mcheck

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arch/x86/kernel/cpu/mcheck/mce.c

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1702,30 +1702,35 @@ static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
17021702
return 0;
17031703
}
17041704

1705-
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1705+
/*
1706+
* Init basic CPU features needed for early decoding of MCEs.
1707+
*/
1708+
static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
17061709
{
1707-
switch (c->x86_vendor) {
1708-
case X86_VENDOR_INTEL:
1709-
mce_intel_feature_init(c);
1710-
mce_adjust_timer = cmci_intel_adjust_timer;
1711-
break;
1712-
1713-
case X86_VENDOR_AMD: {
1710+
if (c->x86_vendor == X86_VENDOR_AMD) {
17141711
mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
17151712
mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
17161713
mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
17171714

1718-
/*
1719-
* Install proper ops for Scalable MCA enabled processors
1720-
*/
17211715
if (mce_flags.smca) {
17221716
msr_ops.ctl = smca_ctl_reg;
17231717
msr_ops.status = smca_status_reg;
17241718
msr_ops.addr = smca_addr_reg;
17251719
msr_ops.misc = smca_misc_reg;
17261720
}
1727-
mce_amd_feature_init(c);
1721+
}
1722+
}
17281723

1724+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1725+
{
1726+
switch (c->x86_vendor) {
1727+
case X86_VENDOR_INTEL:
1728+
mce_intel_feature_init(c);
1729+
mce_adjust_timer = cmci_intel_adjust_timer;
1730+
break;
1731+
1732+
case X86_VENDOR_AMD: {
1733+
mce_amd_feature_init(c);
17291734
break;
17301735
}
17311736

@@ -1812,6 +1817,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
18121817

18131818
machine_check_vector = do_machine_check;
18141819

1820+
__mcheck_cpu_init_early(c);
18151821
__mcheck_cpu_init_generic();
18161822
__mcheck_cpu_init_vendor(c);
18171823
__mcheck_cpu_init_clear_banks();

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