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Jordan Crouserobclark
Jordan Crouse
authored and
robclark
committed
drm/msm: Get rid of the REG_ADRENO offsets
As newer GPU families are added it makes less sense to maintain a "generic" version functions for older families. Move adreno_submit() and get_rptr() into the target specific code for a2xx, a3xx and a4xx. Add a parameter to adreno_flush to pass the target specific WPTR register instead of relying on the generic register. All of this gets rid of the last of the REG_ADRENO offsets so remove all all the register definitions and infrastructure. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
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7 files changed

+178
-234
lines changed

7 files changed

+178
-234
lines changed

‎drivers/gpu/drm/msm/adreno/a2xx_gpu.c‎

Lines changed: 50 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,48 @@ extern bool hang_debug;
1010
static void a2xx_dump(struct msm_gpu *gpu);
1111
static bool a2xx_idle(struct msm_gpu *gpu);
1212

13+
static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
14+
{
15+
struct msm_drm_private *priv = gpu->dev->dev_private;
16+
struct msm_ringbuffer *ring = submit->ring;
17+
unsigned int i;
18+
19+
for (i = 0; i < submit->nr_cmds; i++) {
20+
switch (submit->cmd[i].type) {
21+
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
22+
/* ignore IB-targets */
23+
break;
24+
case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
25+
/* ignore if there has not been a ctx switch: */
26+
if (priv->lastctx == submit->queue->ctx)
27+
break;
28+
fallthrough;
29+
case MSM_SUBMIT_CMD_BUF:
30+
OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
31+
OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
32+
OUT_RING(ring, submit->cmd[i].size);
33+
OUT_PKT2(ring);
34+
break;
35+
}
36+
}
37+
38+
OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
39+
OUT_RING(ring, submit->seqno);
40+
41+
/* wait for idle before cache flush/interrupt */
42+
OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
43+
OUT_RING(ring, 0x00000000);
44+
45+
OUT_PKT3(ring, CP_EVENT_WRITE, 3);
46+
OUT_RING(ring, CACHE_FLUSH_TS);
47+
OUT_RING(ring, rbmemptr(ring, fence));
48+
OUT_RING(ring, submit->seqno);
49+
OUT_PKT3(ring, CP_INTERRUPT, 1);
50+
OUT_RING(ring, 0x80000000);
51+
52+
adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
53+
}
54+
1355
static bool a2xx_me_init(struct msm_gpu *gpu)
1456
{
1557
struct msm_ringbuffer *ring = gpu->rb[0];
@@ -53,7 +95,7 @@ static bool a2xx_me_init(struct msm_gpu *gpu)
5395
OUT_PKT3(ring, CP_SET_PROTECTED_MODE, 1);
5496
OUT_RING(ring, 1);
5597

56-
gpu->funcs->flush(gpu, ring);
98+
adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
5799
return a2xx_idle(gpu);
58100
}
59101

@@ -421,16 +463,11 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
421463
return aspace;
422464
}
423465

424-
/* Register offset defines for A2XX - copy of A3XX */
425-
static const unsigned int a2xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
426-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
427-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI),
428-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
429-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI),
430-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
431-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
432-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
433-
};
466+
static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
467+
{
468+
ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR);
469+
return ring->memptrs->rptr;
470+
}
434471

435472
static const struct adreno_gpu_funcs funcs = {
436473
.base = {
@@ -439,8 +476,7 @@ static const struct adreno_gpu_funcs funcs = {
439476
.pm_suspend = msm_gpu_pm_suspend,
440477
.pm_resume = msm_gpu_pm_resume,
441478
.recover = a2xx_recover,
442-
.submit = adreno_submit,
443-
.flush = adreno_flush,
479+
.submit = a2xx_submit,
444480
.active_ring = adreno_active_ring,
445481
.irq = a2xx_irq,
446482
.destroy = a2xx_destroy,
@@ -450,6 +486,7 @@ static const struct adreno_gpu_funcs funcs = {
450486
.gpu_state_get = a2xx_gpu_state_get,
451487
.gpu_state_put = adreno_gpu_state_put,
452488
.create_address_space = a2xx_create_address_space,
489+
.get_rptr = a2xx_get_rptr,
453490
},
454491
};
455492

@@ -491,8 +528,6 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
491528
else
492529
adreno_gpu->registers = a220_registers;
493530

494-
adreno_gpu->reg_offsets = a2xx_register_offsets;
495-
496531
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
497532
if (ret)
498533
goto fail;

‎drivers/gpu/drm/msm/adreno/a3xx_gpu.c‎

Lines changed: 63 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,61 @@ extern bool hang_debug;
2828
static void a3xx_dump(struct msm_gpu *gpu);
2929
static bool a3xx_idle(struct msm_gpu *gpu);
3030

31+
static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
32+
{
33+
struct msm_drm_private *priv = gpu->dev->dev_private;
34+
struct msm_ringbuffer *ring = submit->ring;
35+
unsigned int i;
36+
37+
for (i = 0; i < submit->nr_cmds; i++) {
38+
switch (submit->cmd[i].type) {
39+
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
40+
/* ignore IB-targets */
41+
break;
42+
case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
43+
/* ignore if there has not been a ctx switch: */
44+
if (priv->lastctx == submit->queue->ctx)
45+
break;
46+
fallthrough;
47+
case MSM_SUBMIT_CMD_BUF:
48+
OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
49+
OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
50+
OUT_RING(ring, submit->cmd[i].size);
51+
OUT_PKT2(ring);
52+
break;
53+
}
54+
}
55+
56+
OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
57+
OUT_RING(ring, submit->seqno);
58+
59+
/* Flush HLSQ lazy updates to make sure there is nothing
60+
* pending for indirect loads after the timestamp has
61+
* passed:
62+
*/
63+
OUT_PKT3(ring, CP_EVENT_WRITE, 1);
64+
OUT_RING(ring, HLSQ_FLUSH);
65+
66+
/* wait for idle before cache flush/interrupt */
67+
OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
68+
OUT_RING(ring, 0x00000000);
69+
70+
/* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
71+
OUT_PKT3(ring, CP_EVENT_WRITE, 3);
72+
OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
73+
OUT_RING(ring, rbmemptr(ring, fence));
74+
OUT_RING(ring, submit->seqno);
75+
76+
#if 0
77+
/* Dummy set-constant to trigger context rollover */
78+
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
79+
OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
80+
OUT_RING(ring, 0x00000000);
81+
#endif
82+
83+
adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
84+
}
85+
3186
static bool a3xx_me_init(struct msm_gpu *gpu)
3287
{
3388
struct msm_ringbuffer *ring = gpu->rb[0];
@@ -51,7 +106,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu)
51106
OUT_RING(ring, 0x00000000);
52107
OUT_RING(ring, 0x00000000);
53108

54-
gpu->funcs->flush(gpu, ring);
109+
adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
55110
return a3xx_idle(gpu);
56111
}
57112

@@ -423,16 +478,11 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu)
423478
return state;
424479
}
425480

426-
/* Register offset defines for A3XX */
427-
static const unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
428-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
429-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI),
430-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
431-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI),
432-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
433-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
434-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
435-
};
481+
static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
482+
{
483+
ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR);
484+
return ring->memptrs->rptr;
485+
}
436486

437487
static const struct adreno_gpu_funcs funcs = {
438488
.base = {
@@ -441,8 +491,7 @@ static const struct adreno_gpu_funcs funcs = {
441491
.pm_suspend = msm_gpu_pm_suspend,
442492
.pm_resume = msm_gpu_pm_resume,
443493
.recover = a3xx_recover,
444-
.submit = adreno_submit,
445-
.flush = adreno_flush,
494+
.submit = a3xx_submit,
446495
.active_ring = adreno_active_ring,
447496
.irq = a3xx_irq,
448497
.destroy = a3xx_destroy,
@@ -452,6 +501,7 @@ static const struct adreno_gpu_funcs funcs = {
452501
.gpu_state_get = a3xx_gpu_state_get,
453502
.gpu_state_put = adreno_gpu_state_put,
454503
.create_address_space = adreno_iommu_create_address_space,
504+
.get_rptr = a3xx_get_rptr,
455505
},
456506
};
457507

@@ -490,7 +540,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
490540
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
491541

492542
adreno_gpu->registers = a3xx_registers;
493-
adreno_gpu->reg_offsets = a3xx_register_offsets;
494543

495544
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
496545
if (ret)

‎drivers/gpu/drm/msm/adreno/a4xx_gpu.c‎

Lines changed: 61 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,54 @@ extern bool hang_debug;
2222
static void a4xx_dump(struct msm_gpu *gpu);
2323
static bool a4xx_idle(struct msm_gpu *gpu);
2424

25+
static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
26+
{
27+
struct msm_drm_private *priv = gpu->dev->dev_private;
28+
struct msm_ringbuffer *ring = submit->ring;
29+
unsigned int i;
30+
31+
for (i = 0; i < submit->nr_cmds; i++) {
32+
switch (submit->cmd[i].type) {
33+
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
34+
/* ignore IB-targets */
35+
break;
36+
case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
37+
/* ignore if there has not been a ctx switch: */
38+
if (priv->lastctx == submit->queue->ctx)
39+
break;
40+
fallthrough;
41+
case MSM_SUBMIT_CMD_BUF:
42+
OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFE, 2);
43+
OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
44+
OUT_RING(ring, submit->cmd[i].size);
45+
OUT_PKT2(ring);
46+
break;
47+
}
48+
}
49+
50+
OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
51+
OUT_RING(ring, submit->seqno);
52+
53+
/* Flush HLSQ lazy updates to make sure there is nothing
54+
* pending for indirect loads after the timestamp has
55+
* passed:
56+
*/
57+
OUT_PKT3(ring, CP_EVENT_WRITE, 1);
58+
OUT_RING(ring, HLSQ_FLUSH);
59+
60+
/* wait for idle before cache flush/interrupt */
61+
OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
62+
OUT_RING(ring, 0x00000000);
63+
64+
/* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
65+
OUT_PKT3(ring, CP_EVENT_WRITE, 3);
66+
OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
67+
OUT_RING(ring, rbmemptr(ring, fence));
68+
OUT_RING(ring, submit->seqno);
69+
70+
adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR);
71+
}
72+
2573
/*
2674
* a4xx_enable_hwcg() - Program the clock control registers
2775
* @device: The adreno device pointer
@@ -129,7 +177,7 @@ static bool a4xx_me_init(struct msm_gpu *gpu)
129177
OUT_RING(ring, 0x00000000);
130178
OUT_RING(ring, 0x00000000);
131179

132-
gpu->funcs->flush(gpu, ring);
180+
adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR);
133181
return a4xx_idle(gpu);
134182
}
135183

@@ -515,17 +563,6 @@ static struct msm_gpu_state *a4xx_gpu_state_get(struct msm_gpu *gpu)
515563
return state;
516564
}
517565

518-
/* Register offset defines for A4XX, in order of enum adreno_regs */
519-
static const unsigned int a4xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
520-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_A4XX_CP_RB_BASE),
521-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI),
522-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_A4XX_CP_RB_RPTR_ADDR),
523-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI),
524-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_A4XX_CP_RB_RPTR),
525-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_A4XX_CP_RB_WPTR),
526-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A4XX_CP_RB_CNTL),
527-
};
528-
529566
static void a4xx_dump(struct msm_gpu *gpu)
530567
{
531568
printk("status: %08x\n",
@@ -576,15 +613,20 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
576613
return 0;
577614
}
578615

616+
static u32 a4xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
617+
{
618+
ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR);
619+
return ring->memptrs->rptr;
620+
}
621+
579622
static const struct adreno_gpu_funcs funcs = {
580623
.base = {
581624
.get_param = adreno_get_param,
582625
.hw_init = a4xx_hw_init,
583626
.pm_suspend = a4xx_pm_suspend,
584627
.pm_resume = a4xx_pm_resume,
585628
.recover = a4xx_recover,
586-
.submit = adreno_submit,
587-
.flush = adreno_flush,
629+
.submit = a4xx_submit,
588630
.active_ring = adreno_active_ring,
589631
.irq = a4xx_irq,
590632
.destroy = a4xx_destroy,
@@ -594,6 +636,7 @@ static const struct adreno_gpu_funcs funcs = {
594636
.gpu_state_get = a4xx_gpu_state_get,
595637
.gpu_state_put = adreno_gpu_state_put,
596638
.create_address_space = adreno_iommu_create_address_space,
639+
.get_rptr = a4xx_get_rptr,
597640
},
598641
.get_timestamp = a4xx_get_timestamp,
599642
};
@@ -631,15 +674,12 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
631674

632675
adreno_gpu->registers = adreno_is_a405(adreno_gpu) ? a405_registers :
633676
a4xx_registers;
634-
adreno_gpu->reg_offsets = a4xx_register_offsets;
635677

636678
/* if needed, allocate gmem: */
637-
if (adreno_is_a4xx(adreno_gpu)) {
638-
ret = adreno_gpu_ocmem_init(dev->dev, adreno_gpu,
639-
&a4xx_gpu->ocmem);
640-
if (ret)
641-
goto fail;
642-
}
679+
ret = adreno_gpu_ocmem_init(dev->dev, adreno_gpu,
680+
&a4xx_gpu->ocmem);
681+
if (ret)
682+
goto fail;
643683

644684
if (!gpu->aspace) {
645685
/* TODO we think it is possible to configure the GPU to

‎drivers/gpu/drm/msm/adreno/a5xx_gpu.c‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1121,17 +1121,6 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
11211121
return IRQ_HANDLED;
11221122
}
11231123

1124-
static const u32 a5xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
1125-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_A5XX_CP_RB_BASE),
1126-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE_HI, REG_A5XX_CP_RB_BASE_HI),
1127-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_A5XX_CP_RB_RPTR_ADDR),
1128-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR_HI,
1129-
REG_A5XX_CP_RB_RPTR_ADDR_HI),
1130-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_A5XX_CP_RB_RPTR),
1131-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_A5XX_CP_RB_WPTR),
1132-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A5XX_CP_RB_CNTL),
1133-
};
1134-
11351124
static const u32 a5xx_registers[] = {
11361125
0x0000, 0x0002, 0x0004, 0x0020, 0x0022, 0x0026, 0x0029, 0x002B,
11371126
0x002E, 0x0035, 0x0038, 0x0042, 0x0044, 0x0044, 0x0047, 0x0095,
@@ -1587,7 +1576,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
15871576
gpu = &adreno_gpu->base;
15881577

15891578
adreno_gpu->registers = a5xx_registers;
1590-
adreno_gpu->reg_offsets = a5xx_register_offsets;
15911579

15921580
a5xx_gpu->lm_leakage = 0x4E001A;
15931581

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