@@ -318,6 +318,15 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
318318 return 0 ;
319319}
320320
321+ /* no mrr support for cards older than 5212 */
322+ static int
323+ ath5k_hw_setup_no_mrr (struct ath5k_hw * ah , struct ath5k_desc * desc ,
324+ unsigned int tx_rate1 , u_int tx_tries1 , u_int tx_rate2 ,
325+ u_int tx_tries2 , unsigned int tx_rate3 , u_int tx_tries3 )
326+ {
327+ return 0 ;
328+ }
329+
321330/*
322331 * Proccess the tx status descriptor on 5210/5211
323332 */
@@ -352,8 +361,10 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
352361 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH );
353362 ts -> ts_antenna = 1 ;
354363 ts -> ts_status = 0 ;
355- ts -> ts_rate = AR5K_REG_MS (tx_ctl -> tx_control_0 ,
364+ ts -> ts_rate [ 0 ] = AR5K_REG_MS (tx_ctl -> tx_control_0 ,
356365 AR5K_2W_TX_DESC_CTL0_XMIT_RATE );
366+ ts -> ts_retry [0 ] = ts -> ts_longretry ;
367+ ts -> ts_final_idx = 0 ;
357368
358369 if (!(tx_status -> tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK )) {
359370 if (tx_status -> tx_status_0 &
@@ -405,29 +416,43 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
405416 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA ) ? 2 : 1 ;
406417 ts -> ts_status = 0 ;
407418
408- switch (AR5K_REG_MS (tx_status -> tx_status_1 ,
409- AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX )) {
410- case 0 :
411- ts -> ts_rate = tx_ctl -> tx_control_3 &
412- AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 ;
413- break ;
419+ ts -> ts_final_idx = AR5K_REG_MS (tx_status -> tx_status_1 ,
420+ AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX );
421+
422+ /* The longretry counter has the number of un-acked retries
423+ * for the final rate. To get the total number of retries
424+ * we have to add the retry counters for the other rates
425+ * as well
426+ */
427+ ts -> ts_retry [ts -> ts_final_idx ] = ts -> ts_longretry ;
428+ switch (ts -> ts_final_idx ) {
429+ case 3 :
430+ ts -> ts_rate [3 ] = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
431+ AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 );
432+
433+ ts -> ts_retry [2 ] = AR5K_REG_MS (tx_ctl -> tx_control_2 ,
434+ AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 );
435+ ts -> ts_longretry += ts -> ts_retry [2 ];
436+ /* fall through */
437+ case 2 :
438+ ts -> ts_rate [2 ] = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
439+ AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 );
440+
441+ ts -> ts_retry [1 ] = AR5K_REG_MS (tx_ctl -> tx_control_2 ,
442+ AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 );
443+ ts -> ts_longretry += ts -> ts_retry [1 ];
444+ /* fall through */
414445 case 1 :
415- ts -> ts_rate = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
446+ ts -> ts_rate [ 1 ] = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
416447 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 );
417- ts -> ts_longretry += AR5K_REG_MS (tx_ctl -> tx_control_2 ,
448+
449+ ts -> ts_retry [0 ] = AR5K_REG_MS (tx_ctl -> tx_control_2 ,
418450 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 );
419- break ;
420- case 2 :
421- ts -> ts_rate = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
422- AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 );
423- ts -> ts_longretry += AR5K_REG_MS (tx_ctl -> tx_control_2 ,
424- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 );
425- break ;
426- case 3 :
427- ts -> ts_rate = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
428- AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 );
429- ts -> ts_longretry += AR5K_REG_MS (tx_ctl -> tx_control_2 ,
430- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 );
451+ ts -> ts_longretry += ts -> ts_retry [0 ];
452+ /* fall through */
453+ case 0 :
454+ ts -> ts_rate [0 ] = tx_ctl -> tx_control_3 &
455+ AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 ;
431456 break ;
432457 }
433458
@@ -653,7 +678,7 @@ int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
653678 } else {
654679 ah -> ah_setup_rx_desc = ath5k_hw_setup_rx_desc ;
655680 ah -> ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc ;
656- ah -> ah_setup_mrr_tx_desc = ath5k_hw_setup_mrr_tx_desc ;
681+ ah -> ah_setup_mrr_tx_desc = ath5k_hw_setup_no_mrr ;
657682 ah -> ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status ;
658683 }
659684
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