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Georgi Djakovbebarino
Georgi Djakov
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bebarino
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clk: qcom: Introduce parent_map tables
In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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15 files changed

+338
-286
lines changed

15 files changed

+338
-286
lines changed

‎drivers/clk/qcom/clk-rcg.c‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw)
5454
goto err;
5555
ns = ns_to_src(&rcg->s, ns);
5656
for (i = 0; i < num_parents; i++)
57-
if (ns == rcg->s.parent_map[i])
57+
if (ns == rcg->s.parent_map[i].cfg)
5858
return i;
5959

6060
err:
@@ -90,7 +90,7 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
9090
ns = ns_to_src(s, ns);
9191

9292
for (i = 0; i < num_parents; i++)
93-
if (ns == s->parent_map[i])
93+
if (ns == s->parent_map[i].cfg)
9494
return i;
9595

9696
err:
@@ -105,7 +105,7 @@ static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
105105
u32 ns;
106106

107107
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
108-
ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns);
108+
ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
109109
regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
110110

111111
return 0;
@@ -206,7 +206,7 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
206206
static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
207207
{
208208
u32 ns, md, reg;
209-
int bank, new_bank, ret;
209+
int bank, new_bank, ret, index;
210210
struct mn *mn;
211211
struct pre_div *p;
212212
struct src_sel *s;
@@ -276,7 +276,10 @@ static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
276276
}
277277

278278
s = &rcg->s[new_bank];
279-
ns = src_to_ns(s, s->parent_map[f->src], ns);
279+
index = qcom_find_src_index(hw, s->parent_map, f->src);
280+
if (index < 0)
281+
return index;
282+
ns = src_to_ns(s, s->parent_map[index].cfg, ns);
280283
ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
281284
if (ret)
282285
return ret;

‎drivers/clk/qcom/clk-rcg.h‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,16 @@ struct freq_tbl {
2525
u16 n;
2626
};
2727

28+
/**
29+
* struct parent_map - map table for PLL source select configuration values
30+
* @src: source PLL
31+
* @cfg: configuration value
32+
*/
33+
struct parent_map {
34+
u8 src;
35+
u8 cfg;
36+
};
37+
2838
/**
2939
* struct mn - M/N:D counter
3040
* @mnctr_en_bit: bit to enable mn counter
@@ -65,7 +75,7 @@ struct pre_div {
6575
struct src_sel {
6676
u8 src_sel_shift;
6777
#define SRC_SEL_MASK 0x7
68-
const u8 *parent_map;
78+
const struct parent_map *parent_map;
6979
};
7080

7181
/**
@@ -151,7 +161,7 @@ struct clk_rcg2 {
151161
u32 cmd_rcgr;
152162
u8 mnd_width;
153163
u8 hid_width;
154-
const u8 *parent_map;
164+
const struct parent_map *parent_map;
155165
const struct freq_tbl *freq_tbl;
156166
struct clk_regmap clkr;
157167
};

‎drivers/clk/qcom/clk-rcg2.c‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
7575
cfg >>= CFG_SRC_SEL_SHIFT;
7676

7777
for (i = 0; i < num_parents; i++)
78-
if (cfg == rcg->parent_map[i])
78+
if (cfg == rcg->parent_map[i].cfg)
7979
return i;
8080

8181
err:
@@ -114,10 +114,10 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
114114
{
115115
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
116116
int ret;
117+
u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
117118

118119
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
119-
CFG_SRC_SEL_MASK,
120-
rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
120+
CFG_SRC_SEL_MASK, cfg);
121121
if (ret)
122122
return ret;
123123

@@ -222,7 +222,11 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
222222
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
223223
{
224224
u32 cfg, mask;
225-
int ret;
225+
struct clk_hw *hw = &rcg->clkr.hw;
226+
int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
227+
228+
if (index < 0)
229+
return index;
226230

227231
if (rcg->mnd_width && f->n) {
228232
mask = BIT(rcg->mnd_width) - 1;
@@ -245,7 +249,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
245249
mask = BIT(rcg->hid_width) - 1;
246250
mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
247251
cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
248-
cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
252+
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
249253
if (rcg->mnd_width && f->n && (f->m != f->n))
250254
cfg |= CFG_MODE_DUAL_EDGE;
251255
ret = regmap_update_bits(rcg->clkr.regmap,

‎drivers/clk/qcom/common.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,18 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
4343
}
4444
EXPORT_SYMBOL_GPL(qcom_find_freq);
4545

46+
int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
47+
{
48+
int i, num_parents = __clk_get_num_parents(hw->clk);
49+
50+
for (i = 0; i < num_parents; i++)
51+
if (src == map[i].src)
52+
return i;
53+
54+
return -ENOENT;
55+
}
56+
EXPORT_SYMBOL_GPL(qcom_find_src_index);
57+
4658
struct regmap *
4759
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
4860
{

‎drivers/clk/qcom/common.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@ struct clk_regmap;
1919
struct qcom_reset_map;
2020
struct regmap;
2121
struct freq_tbl;
22+
struct clk_hw;
23+
struct parent_map;
2224

2325
struct qcom_cc_desc {
2426
const struct regmap_config *config;
@@ -30,6 +32,8 @@ struct qcom_cc_desc {
3032

3133
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
3234
unsigned long rate);
35+
extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
36+
u8 src);
3337

3438
extern struct regmap *qcom_cc_map(struct platform_device *pdev,
3539
const struct qcom_cc_desc *desc);

‎drivers/clk/qcom/gcc-apq8084.c‎

Lines changed: 32 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -32,29 +32,31 @@
3232
#include "clk-branch.h"
3333
#include "reset.h"
3434

35-
#define P_XO 0
36-
#define P_GPLL0 1
37-
#define P_GPLL1 1
38-
#define P_GPLL4 2
39-
#define P_PCIE_0_1_PIPE_CLK 1
40-
#define P_SATA_ASIC0_CLK 1
41-
#define P_SATA_RX_CLK 1
42-
#define P_SLEEP_CLK 1
35+
enum {
36+
P_XO,
37+
P_GPLL0,
38+
P_GPLL1,
39+
P_GPLL4,
40+
P_PCIE_0_1_PIPE_CLK,
41+
P_SATA_ASIC0_CLK,
42+
P_SATA_RX_CLK,
43+
P_SLEEP_CLK,
44+
};
4345

44-
static const u8 gcc_xo_gpll0_map[] = {
45-
[P_XO] = 0,
46-
[P_GPLL0] = 1,
46+
static const struct parent_map gcc_xo_gpll0_map[] = {
47+
{ P_XO, 0 },
48+
{ P_GPLL0, 1 }
4749
};
4850

4951
static const char *gcc_xo_gpll0[] = {
5052
"xo",
5153
"gpll0_vote",
5254
};
5355

54-
static const u8 gcc_xo_gpll0_gpll4_map[] = {
55-
[P_XO] = 0,
56-
[P_GPLL0] = 1,
57-
[P_GPLL4] = 5,
56+
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
57+
{ P_XO, 0 },
58+
{ P_GPLL0, 1 },
59+
{ P_GPLL4, 5 }
5860
};
5961

6062
static const char *gcc_xo_gpll0_gpll4[] = {
@@ -63,39 +65,39 @@ static const char *gcc_xo_gpll0_gpll4[] = {
6365
"gpll4_vote",
6466
};
6567

66-
static const u8 gcc_xo_sata_asic0_map[] = {
67-
[P_XO] = 0,
68-
[P_SATA_ASIC0_CLK] = 2,
68+
static const struct parent_map gcc_xo_sata_asic0_map[] = {
69+
{ P_XO, 0 },
70+
{ P_SATA_ASIC0_CLK, 2 }
6971
};
7072

7173
static const char *gcc_xo_sata_asic0[] = {
7274
"xo",
7375
"sata_asic0_clk",
7476
};
7577

76-
static const u8 gcc_xo_sata_rx_map[] = {
77-
[P_XO] = 0,
78-
[P_SATA_RX_CLK] = 2,
78+
static const struct parent_map gcc_xo_sata_rx_map[] = {
79+
{ P_XO, 0 },
80+
{ P_SATA_RX_CLK, 2}
7981
};
8082

8183
static const char *gcc_xo_sata_rx[] = {
8284
"xo",
8385
"sata_rx_clk",
8486
};
8587

86-
static const u8 gcc_xo_pcie_map[] = {
87-
[P_XO] = 0,
88-
[P_PCIE_0_1_PIPE_CLK] = 2,
88+
static const struct parent_map gcc_xo_pcie_map[] = {
89+
{ P_XO, 0 },
90+
{ P_PCIE_0_1_PIPE_CLK, 2 }
8991
};
9092

9193
static const char *gcc_xo_pcie[] = {
9294
"xo",
9395
"pcie_pipe",
9496
};
9597

96-
static const u8 gcc_xo_pcie_sleep_map[] = {
97-
[P_XO] = 0,
98-
[P_SLEEP_CLK] = 6,
98+
static const struct parent_map gcc_xo_pcie_sleep_map[] = {
99+
{ P_XO, 0 },
100+
{ P_SLEEP_CLK, 6 }
99101
};
100102

101103
static const char *gcc_xo_pcie_sleep[] = {
@@ -1263,9 +1265,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
12631265
{ }
12641266
};
12651267

1266-
static u8 usb_hsic_clk_src_map[] = {
1267-
[P_XO] = 0,
1268-
[P_GPLL1] = 4,
1268+
static const struct parent_map usb_hsic_clk_src_map[] = {
1269+
{ P_XO, 0 },
1270+
{ P_GPLL1, 4 }
12691271
};
12701272

12711273
static struct clk_rcg2 usb_hsic_clk_src = {

‎drivers/clk/qcom/gcc-ipq806x.c‎

Lines changed: 24 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -140,26 +140,28 @@ static struct clk_regmap pll14_vote = {
140140
},
141141
};
142142

143-
#define P_PXO 0
144-
#define P_PLL8 1
145-
#define P_PLL3 1
146-
#define P_PLL0 2
147-
#define P_CXO 2
143+
enum {
144+
P_PXO,
145+
P_PLL8,
146+
P_PLL3,
147+
P_PLL0,
148+
P_CXO,
149+
};
148150

149-
static const u8 gcc_pxo_pll8_map[] = {
150-
[P_PXO] = 0,
151-
[P_PLL8] = 3,
151+
static const struct parent_map gcc_pxo_pll8_map[] = {
152+
{ P_PXO, 0 },
153+
{ P_PLL8, 3 }
152154
};
153155

154156
static const char *gcc_pxo_pll8[] = {
155157
"pxo",
156158
"pll8_vote",
157159
};
158160

159-
static const u8 gcc_pxo_pll8_cxo_map[] = {
160-
[P_PXO] = 0,
161-
[P_PLL8] = 3,
162-
[P_CXO] = 5,
161+
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
162+
{ P_PXO, 0 },
163+
{ P_PLL8, 3 },
164+
{ P_CXO, 5 }
163165
};
164166

165167
static const char *gcc_pxo_pll8_cxo[] = {
@@ -168,25 +170,25 @@ static const char *gcc_pxo_pll8_cxo[] = {
168170
"cxo",
169171
};
170172

171-
static const u8 gcc_pxo_pll3_map[] = {
172-
[P_PXO] = 0,
173-
[P_PLL3] = 1,
173+
static const struct parent_map gcc_pxo_pll3_map[] = {
174+
{ P_PXO, 0 },
175+
{ P_PLL3, 1 }
174176
};
175177

176-
static const u8 gcc_pxo_pll3_sata_map[] = {
177-
[P_PXO] = 0,
178-
[P_PLL3] = 6,
178+
static const struct parent_map gcc_pxo_pll3_sata_map[] = {
179+
{ P_PXO, 0 },
180+
{ P_PLL3, 6 }
179181
};
180182

181183
static const char *gcc_pxo_pll3[] = {
182184
"pxo",
183185
"pll3",
184186
};
185187

186-
static const u8 gcc_pxo_pll8_pll0[] = {
187-
[P_PXO] = 0,
188-
[P_PLL8] = 3,
189-
[P_PLL0] = 2,
188+
static const struct parent_map gcc_pxo_pll8_pll0[] = {
189+
{ P_PXO, 0 },
190+
{ P_PLL8, 3 },
191+
{ P_PLL0, 2 }
190192
};
191193

192194
static const char *gcc_pxo_pll8_pll0_map[] = {

‎drivers/clk/qcom/gcc-msm8660.c‎

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -59,24 +59,26 @@ static struct clk_regmap pll8_vote = {
5959
},
6060
};
6161

62-
#define P_PXO 0
63-
#define P_PLL8 1
64-
#define P_CXO 2
62+
enum {
63+
P_PXO,
64+
P_PLL8,
65+
P_CXO,
66+
};
6567

66-
static const u8 gcc_pxo_pll8_map[] = {
67-
[P_PXO] = 0,
68-
[P_PLL8] = 3,
68+
static const struct parent_map gcc_pxo_pll8_map[] = {
69+
{ P_PXO, 0 },
70+
{ P_PLL8, 3 }
6971
};
7072

7173
static const char *gcc_pxo_pll8[] = {
7274
"pxo",
7375
"pll8_vote",
7476
};
7577

76-
static const u8 gcc_pxo_pll8_cxo_map[] = {
77-
[P_PXO] = 0,
78-
[P_PLL8] = 3,
79-
[P_CXO] = 5,
78+
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
79+
{ P_PXO, 0 },
80+
{ P_PLL8, 3 },
81+
{ P_CXO, 5 }
8082
};
8183

8284
static const char *gcc_pxo_pll8_cxo[] = {

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