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Matthew Wilcoxjbarnes993
Matthew Wilcox
authored and
jbarnes993
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PCI MSI: Replace 'type' with 'is_msix'
By changing from a 5-bit field to a 1-bit field, we free up some bits that can be used by a later patch. Also rearrange the fields for better packing on 64-bit platforms (reducing the size of msi_desc from 72 bytes to 64 bytes). Signed-off-by: Matthew Wilcox <[email protected]> Signed-off-by: Jesse Barnes <[email protected]>
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-78
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2 files changed

+41
-78
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‎drivers/pci/msi.c‎

Lines changed: 39 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -111,20 +111,10 @@ static void msix_flush_writes(struct irq_desc *desc)
111111

112112
entry = get_irq_desc_msi(desc);
113113
BUG_ON(!entry || !entry->dev);
114-
switch (entry->msi_attrib.type) {
115-
case PCI_CAP_ID_MSI:
116-
/* nothing to do */
117-
break;
118-
case PCI_CAP_ID_MSIX:
119-
{
114+
if (entry->msi_attrib.is_msix) {
120115
int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
121116
PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
122117
readl(entry->mask_base + offset);
123-
break;
124-
}
125-
default:
126-
BUG();
127-
break;
128118
}
129119
}
130120

@@ -143,32 +133,23 @@ static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag)
143133

144134
entry = get_irq_desc_msi(desc);
145135
BUG_ON(!entry || !entry->dev);
146-
switch (entry->msi_attrib.type) {
147-
case PCI_CAP_ID_MSI:
148-
if (entry->msi_attrib.maskbit) {
149-
int pos;
150-
u32 mask_bits;
151-
152-
pos = (long)entry->mask_base;
153-
pci_read_config_dword(entry->dev, pos, &mask_bits);
154-
mask_bits &= ~(mask);
155-
mask_bits |= flag & mask;
156-
pci_write_config_dword(entry->dev, pos, mask_bits);
157-
} else {
158-
return 0;
159-
}
160-
break;
161-
case PCI_CAP_ID_MSIX:
162-
{
136+
if (entry->msi_attrib.is_msix) {
163137
int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
164138
PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
165139
writel(flag, entry->mask_base + offset);
166140
readl(entry->mask_base + offset);
167-
break;
168-
}
169-
default:
170-
BUG();
171-
break;
141+
} else {
142+
int pos;
143+
u32 mask_bits;
144+
145+
if (!entry->msi_attrib.maskbit)
146+
return 0;
147+
148+
pos = (long)entry->mask_base;
149+
pci_read_config_dword(entry->dev, pos, &mask_bits);
150+
mask_bits &= ~mask;
151+
mask_bits |= flag & mask;
152+
pci_write_config_dword(entry->dev, pos, mask_bits);
172153
}
173154
entry->msi_attrib.masked = !!flag;
174155
return 1;
@@ -177,9 +158,14 @@ static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag)
177158
void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
178159
{
179160
struct msi_desc *entry = get_irq_desc_msi(desc);
180-
switch(entry->msi_attrib.type) {
181-
case PCI_CAP_ID_MSI:
182-
{
161+
if (entry->msi_attrib.is_msix) {
162+
void __iomem *base = entry->mask_base +
163+
entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
164+
165+
msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
166+
msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
167+
msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
168+
} else {
183169
struct pci_dev *dev = entry->dev;
184170
int pos = entry->msi_attrib.pos;
185171
u16 data;
@@ -195,21 +181,6 @@ void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
195181
pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
196182
}
197183
msg->data = data;
198-
break;
199-
}
200-
case PCI_CAP_ID_MSIX:
201-
{
202-
void __iomem *base;
203-
base = entry->mask_base +
204-
entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
205-
206-
msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
207-
msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
208-
msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
209-
break;
210-
}
211-
default:
212-
BUG();
213184
}
214185
}
215186

@@ -223,9 +194,17 @@ void read_msi_msg(unsigned int irq, struct msi_msg *msg)
223194
void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
224195
{
225196
struct msi_desc *entry = get_irq_desc_msi(desc);
226-
switch (entry->msi_attrib.type) {
227-
case PCI_CAP_ID_MSI:
228-
{
197+
if (entry->msi_attrib.is_msix) {
198+
void __iomem *base;
199+
base = entry->mask_base +
200+
entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
201+
202+
writel(msg->address_lo,
203+
base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
204+
writel(msg->address_hi,
205+
base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
206+
writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
207+
} else {
229208
struct pci_dev *dev = entry->dev;
230209
int pos = entry->msi_attrib.pos;
231210

@@ -240,23 +219,6 @@ void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
240219
pci_write_config_word(dev, msi_data_reg(pos, 0),
241220
msg->data);
242221
}
243-
break;
244-
}
245-
case PCI_CAP_ID_MSIX:
246-
{
247-
void __iomem *base;
248-
base = entry->mask_base +
249-
entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
250-
251-
writel(msg->address_lo,
252-
base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
253-
writel(msg->address_hi,
254-
base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
255-
writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
256-
break;
257-
}
258-
default:
259-
BUG();
260222
}
261223
entry->msg = *msg;
262224
}
@@ -393,7 +355,7 @@ static int msi_capability_init(struct pci_dev *dev)
393355
if (!entry)
394356
return -ENOMEM;
395357

396-
entry->msi_attrib.type = PCI_CAP_ID_MSI;
358+
entry->msi_attrib.is_msix = 0;
397359
entry->msi_attrib.is_64 = is_64bit_address(control);
398360
entry->msi_attrib.entry_nr = 0;
399361
entry->msi_attrib.maskbit = is_mask_bit_support(control);
@@ -475,7 +437,7 @@ static int msix_capability_init(struct pci_dev *dev,
475437
break;
476438

477439
j = entries[i].entry;
478-
entry->msi_attrib.type = PCI_CAP_ID_MSIX;
440+
entry->msi_attrib.is_msix = 1;
479441
entry->msi_attrib.is_64 = 1;
480442
entry->msi_attrib.entry_nr = j;
481443
entry->msi_attrib.maskbit = 1;
@@ -619,12 +581,13 @@ void pci_msi_shutdown(struct pci_dev* dev)
619581
struct irq_desc *desc = irq_to_desc(dev->irq);
620582
msi_set_mask_bits(desc, mask, ~mask);
621583
}
622-
if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI)
584+
if (!entry->dev || entry->msi_attrib.is_msix)
623585
return;
624586

625587
/* Restore dev->irq to its default pin-assertion irq */
626588
dev->irq = entry->msi_attrib.default_irq;
627589
}
590+
628591
void pci_disable_msi(struct pci_dev* dev)
629592
{
630593
struct msi_desc *entry;
@@ -635,7 +598,7 @@ void pci_disable_msi(struct pci_dev* dev)
635598
pci_msi_shutdown(dev);
636599

637600
entry = list_entry(dev->msi_list.next, struct msi_desc, list);
638-
if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI)
601+
if (!entry->dev || entry->msi_attrib.is_msix)
639602
return;
640603

641604
msi_free_irqs(dev);
@@ -654,7 +617,7 @@ static int msi_free_irqs(struct pci_dev* dev)
654617
arch_teardown_msi_irqs(dev);
655618

656619
list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
657-
if (entry->msi_attrib.type == PCI_CAP_ID_MSIX) {
620+
if (entry->msi_attrib.is_msix) {
658621
writel(1, entry->mask_base + entry->msi_attrib.entry_nr
659622
* PCI_MSIX_ENTRY_SIZE
660623
+ PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);

‎include/linux/msi.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,13 +20,13 @@ extern void write_msi_msg(unsigned int irq, struct msi_msg *msg);
2020

2121
struct msi_desc {
2222
struct {
23-
__u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
23+
__u8 is_msix : 1;
2424
__u8 maskbit : 1; /* mask-pending bit supported ? */
2525
__u8 masked : 1;
2626
__u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */
2727
__u8 pos; /* Location of the msi capability */
28-
__u32 maskbits_mask; /* mask bits mask */
2928
__u16 entry_nr; /* specific enabled entry */
29+
__u32 maskbits_mask; /* mask bits mask */
3030
unsigned default_irq; /* default pre-assigned irq */
3131
}msi_attrib;
3232

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