@@ -1733,29 +1733,15 @@ static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
17331733 (__be64 __iomem * )pe -> phb -> ioda .tce_inval_reg_phys :
17341734 pe -> phb -> ioda .tce_inval_reg ;
17351735 unsigned long start , end , inc ;
1736- const unsigned shift = tbl -> it_page_shift ;
17371736
17381737 start = __pa (((__be64 * )tbl -> it_base ) + index - tbl -> it_offset );
17391738 end = __pa (((__be64 * )tbl -> it_base ) + index - tbl -> it_offset +
17401739 npages - 1 );
17411740
1742- /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1743- if (tbl -> it_busno ) {
1744- start <<= shift ;
1745- end <<= shift ;
1746- inc = 128ull << shift ;
1747- start |= tbl -> it_busno ;
1748- end |= tbl -> it_busno ;
1749- } else if (tbl -> it_type & TCE_PCI_SWINV_PAIR ) {
1750- /* p7ioc-style invalidation, 2 TCEs per write */
1751- start |= (1ull << 63 );
1752- end |= (1ull << 63 );
1753- inc = 16 ;
1754- } else {
1755- /* Default (older HW) */
1756- inc = 128 ;
1757- }
1758-
1741+ /* p7ioc-style invalidation, 2 TCEs per write */
1742+ start |= (1ull << 63 );
1743+ end |= (1ull << 63 );
1744+ inc = 16 ;
17591745 end |= inc - 1 ; /* round up end to be different than start */
17601746
17611747 mb (); /* Ensure above stores are visible */
@@ -1781,7 +1767,7 @@ static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
17811767 int ret = pnv_tce_build (tbl , index , npages , uaddr , direction ,
17821768 attrs );
17831769
1784- if (!ret && ( tbl -> it_type & TCE_PCI_SWINV_CREATE ) )
1770+ if (!ret )
17851771 pnv_pci_p7ioc_tce_invalidate (tbl , index , npages , false);
17861772
17871773 return ret ;
@@ -1793,8 +1779,7 @@ static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
17931779{
17941780 long ret = pnv_tce_xchg (tbl , index , hpa , direction );
17951781
1796- if (!ret && (tbl -> it_type &
1797- (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE )))
1782+ if (!ret )
17981783 pnv_pci_p7ioc_tce_invalidate (tbl , index , 1 , false);
17991784
18001785 return ret ;
@@ -1806,8 +1791,7 @@ static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
18061791{
18071792 pnv_tce_free (tbl , index , npages );
18081793
1809- if (tbl -> it_type & TCE_PCI_SWINV_FREE )
1810- pnv_pci_p7ioc_tce_invalidate (tbl , index , npages , false);
1794+ pnv_pci_p7ioc_tce_invalidate (tbl , index , npages , false);
18111795}
18121796
18131797static struct iommu_table_ops pnv_ioda1_iommu_ops = {
@@ -1910,7 +1894,7 @@ static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
19101894 int ret = pnv_tce_build (tbl , index , npages , uaddr , direction ,
19111895 attrs );
19121896
1913- if (!ret && ( tbl -> it_type & TCE_PCI_SWINV_CREATE ) )
1897+ if (!ret )
19141898 pnv_pci_ioda2_tce_invalidate (tbl , index , npages , false);
19151899
19161900 return ret ;
@@ -1922,8 +1906,7 @@ static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
19221906{
19231907 long ret = pnv_tce_xchg (tbl , index , hpa , direction );
19241908
1925- if (!ret && (tbl -> it_type &
1926- (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE )))
1909+ if (!ret )
19271910 pnv_pci_ioda2_tce_invalidate (tbl , index , 1 , false);
19281911
19291912 return ret ;
@@ -1935,8 +1918,7 @@ static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
19351918{
19361919 pnv_tce_free (tbl , index , npages );
19371920
1938- if (tbl -> it_type & TCE_PCI_SWINV_FREE )
1939- pnv_pci_ioda2_tce_invalidate (tbl , index , npages , false);
1921+ pnv_pci_ioda2_tce_invalidate (tbl , index , npages , false);
19401922}
19411923
19421924static void pnv_ioda2_table_free (struct iommu_table * tbl )
@@ -2105,12 +2087,6 @@ static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
21052087 base * PNV_IODA1_DMA32_SEGSIZE ,
21062088 IOMMU_PAGE_SHIFT_4K );
21072089
2108- /* OPAL variant of P7IOC SW invalidated TCEs */
2109- if (phb -> ioda .tce_inval_reg )
2110- tbl -> it_type |= (TCE_PCI_SWINV_CREATE |
2111- TCE_PCI_SWINV_FREE |
2112- TCE_PCI_SWINV_PAIR );
2113-
21142090 tbl -> it_ops = & pnv_ioda1_iommu_ops ;
21152091 pe -> table_group .tce32_start = tbl -> it_offset << tbl -> it_page_shift ;
21162092 pe -> table_group .tce32_size = tbl -> it_size << tbl -> it_page_shift ;
@@ -2233,8 +2209,6 @@ static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
22332209 }
22342210
22352211 tbl -> it_ops = & pnv_ioda2_iommu_ops ;
2236- if (pe -> phb -> ioda .tce_inval_reg )
2237- tbl -> it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE );
22382212
22392213 * ptbl = tbl ;
22402214
@@ -2283,10 +2257,6 @@ static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
22832257 if (!pnv_iommu_bypass_disabled )
22842258 pnv_pci_ioda2_set_bypass (pe , true);
22852259
2286- /* OPAL variant of PHB3 invalidated TCEs */
2287- if (pe -> phb -> ioda .tce_inval_reg )
2288- tbl -> it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE );
2289-
22902260 /*
22912261 * Setting table base here only for carrying iommu_group
22922262 * further down to let iommu_add_device() do the job.
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