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rodrigovivirodrigovivi
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drm/i915/cnl: Add registers related to voltage swing sequences.
This are the registers and bits needed for the voltage swing sequence on Cannonlake. v2: Remove CL_DW5 that was wrongly defined. v3: Use (1 << 1) instead of (1<<1) as Paulo suggested Change DW2 swing sel upper and lower macros to do the bit selection instead of definint a table that doesn't match the spec. It is based on a Manasi version of it. Credits-to: Manasi. v4: Let SCALING_MODE_SEL flexible. (Manasi) Cc: Paulo Zanoni <[email protected]> Cc: Manasi Navare <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎drivers/gpu/drm/i915/i915_reg.h‎

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@@ -1693,6 +1693,146 @@ enum skl_disp_power_wells {
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#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
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#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
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#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
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#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
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#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
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#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
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#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
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#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
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#define _CNL_PORT_PCS_DW1_LN0_B 0x162604
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#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
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#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
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#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
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#define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_PCS_DW1_GRP_AE, \
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_CNL_PORT_PCS_DW1_GRP_B, \
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_CNL_PORT_PCS_DW1_GRP_C, \
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_CNL_PORT_PCS_DW1_GRP_D, \
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_CNL_PORT_PCS_DW1_GRP_AE, \
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_CNL_PORT_PCS_DW1_GRP_F)
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#define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \
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_CNL_PORT_PCS_DW1_LN0_AE, \
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_CNL_PORT_PCS_DW1_LN0_B, \
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_CNL_PORT_PCS_DW1_LN0_C, \
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_CNL_PORT_PCS_DW1_LN0_D, \
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_CNL_PORT_PCS_DW1_LN0_AE, \
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_CNL_PORT_PCS_DW1_LN0_F)
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#define COMMON_KEEPER_EN (1 << 26)
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#define _CNL_PORT_TX_DW2_GRP_AE 0x162348
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#define _CNL_PORT_TX_DW2_GRP_B 0x1623C8
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#define _CNL_PORT_TX_DW2_GRP_C 0x162B48
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#define _CNL_PORT_TX_DW2_GRP_D 0x162BC8
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#define _CNL_PORT_TX_DW2_GRP_F 0x162A48
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#define _CNL_PORT_TX_DW2_LN0_AE 0x162448
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#define _CNL_PORT_TX_DW2_LN0_B 0x162648
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#define _CNL_PORT_TX_DW2_LN0_C 0x162C48
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#define _CNL_PORT_TX_DW2_LN0_D 0x162E48
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#define _CNL_PORT_TX_DW2_LN0_F 0x162A48
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#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW2_GRP_AE, \
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_CNL_PORT_TX_DW2_GRP_B, \
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_CNL_PORT_TX_DW2_GRP_C, \
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_CNL_PORT_TX_DW2_GRP_D, \
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_CNL_PORT_TX_DW2_GRP_AE, \
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_CNL_PORT_TX_DW2_GRP_F)
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#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW2_LN0_AE, \
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_CNL_PORT_TX_DW2_LN0_B, \
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_CNL_PORT_TX_DW2_LN0_C, \
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_CNL_PORT_TX_DW2_LN0_D, \
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_CNL_PORT_TX_DW2_LN0_AE, \
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_CNL_PORT_TX_DW2_LN0_F)
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#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
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#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
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#define RCOMP_SCALAR(x) ((x) << 0)
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#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
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#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
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#define _CNL_PORT_TX_DW4_GRP_C 0x162B50
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#define _CNL_PORT_TX_DW4_GRP_D 0x162BD0
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#define _CNL_PORT_TX_DW4_GRP_F 0x162A50
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#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
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#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
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#define _CNL_PORT_TX_DW4_LN0_B 0x162650
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#define _CNL_PORT_TX_DW4_LN0_C 0x162C50
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#define _CNL_PORT_TX_DW4_LN0_D 0x162E50
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#define _CNL_PORT_TX_DW4_LN0_F 0x162850
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#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW4_GRP_AE, \
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_CNL_PORT_TX_DW4_GRP_B, \
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_CNL_PORT_TX_DW4_GRP_C, \
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_CNL_PORT_TX_DW4_GRP_D, \
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_CNL_PORT_TX_DW4_GRP_AE, \
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_CNL_PORT_TX_DW4_GRP_F)
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#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \
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_CNL_PORT_TX_DW4_LN0_AE, \
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_CNL_PORT_TX_DW4_LN1_AE, \
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_CNL_PORT_TX_DW4_LN0_B, \
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_CNL_PORT_TX_DW4_LN0_C, \
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_CNL_PORT_TX_DW4_LN0_D, \
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_CNL_PORT_TX_DW4_LN0_AE, \
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_CNL_PORT_TX_DW4_LN0_F)
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#define LOADGEN_SELECT (1 << 31)
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#define POST_CURSOR_1(x) ((x) << 12)
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#define POST_CURSOR_2(x) ((x) << 6)
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#define CURSOR_COEFF(x) ((x) << 0)
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#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
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#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
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#define _CNL_PORT_TX_DW5_GRP_C 0x162B54
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#define _CNL_PORT_TX_DW5_GRP_D 0x162BD4
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#define _CNL_PORT_TX_DW5_GRP_F 0x162A54
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#define _CNL_PORT_TX_DW5_LN0_AE 0x162454
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#define _CNL_PORT_TX_DW5_LN0_B 0x162654
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#define _CNL_PORT_TX_DW5_LN0_C 0x162C54
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#define _CNL_PORT_TX_DW5_LN0_D 0x162ED4
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#define _CNL_PORT_TX_DW5_LN0_F 0x162854
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#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW5_GRP_AE, \
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_CNL_PORT_TX_DW5_GRP_B, \
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_CNL_PORT_TX_DW5_GRP_C, \
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_CNL_PORT_TX_DW5_GRP_D, \
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_CNL_PORT_TX_DW5_GRP_AE, \
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_CNL_PORT_TX_DW5_GRP_F)
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#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW5_LN0_AE, \
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_CNL_PORT_TX_DW5_LN0_B, \
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_CNL_PORT_TX_DW5_LN0_C, \
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_CNL_PORT_TX_DW5_LN0_D, \
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_CNL_PORT_TX_DW5_LN0_AE, \
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_CNL_PORT_TX_DW5_LN0_F)
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#define TX_TRAINING_EN (1 << 31)
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#define TAP3_DISABLE (1 << 29)
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#define SCALING_MODE_SEL(x) ((x) << 18)
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#define RTERM_SELECT(x) ((x) << 3)
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#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
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#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
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#define _CNL_PORT_TX_DW7_GRP_C 0x162B5C
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#define _CNL_PORT_TX_DW7_GRP_D 0x162BDC
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#define _CNL_PORT_TX_DW7_GRP_F 0x162A5C
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#define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
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#define _CNL_PORT_TX_DW7_LN0_B 0x16265C
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#define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
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#define _CNL_PORT_TX_DW7_LN0_D 0x162EDC
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#define _CNL_PORT_TX_DW7_LN0_F 0x16285C
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#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW7_GRP_AE, \
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_CNL_PORT_TX_DW7_GRP_B, \
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_CNL_PORT_TX_DW7_GRP_C, \
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_CNL_PORT_TX_DW7_GRP_D, \
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_CNL_PORT_TX_DW7_GRP_AE, \
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_CNL_PORT_TX_DW7_GRP_F)
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#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW7_LN0_AE, \
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_CNL_PORT_TX_DW7_LN0_B, \
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_CNL_PORT_TX_DW7_LN0_C, \
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_CNL_PORT_TX_DW7_LN0_D, \
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_CNL_PORT_TX_DW7_LN0_AE, \
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_CNL_PORT_TX_DW7_LN0_F)
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#define N_SCALAR(x) ((x) << 24)
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/* The spec defines this only for BXT PHY0, but lets assume that this
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* would exist for PHY1 too if it had a second channel.
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*/

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