@@ -490,14 +490,9 @@ static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
490490static int mx51_ecspi_prepare_message (struct spi_imx_data * spi_imx ,
491491 struct spi_message * msg )
492492{
493- return 0 ;
494- }
495-
496- static int mx51_ecspi_config (struct spi_device * spi )
497- {
498- struct spi_imx_data * spi_imx = spi_master_get_devdata (spi -> master );
493+ struct spi_device * spi = msg -> spi ;
499494 u32 ctrl = MX51_ECSPI_CTRL_ENABLE ;
500- u32 clk = spi_imx -> speed_hz , delay , reg ;
495+ u32 testreg ;
501496 u32 cfg = readl (spi_imx -> base + MX51_ECSPI_CONFIG );
502497
503498 /* set Master or Slave mode */
@@ -512,19 +507,21 @@ static int mx51_ecspi_config(struct spi_device *spi)
512507 if (spi -> mode & SPI_READY )
513508 ctrl |= MX51_ECSPI_CTRL_DRCTL (spi_imx -> spi_drctl );
514509
515- /* set clock speed */
516- ctrl |= mx51_ecspi_clkdiv (spi_imx , spi_imx -> speed_hz , & clk );
517- spi_imx -> spi_bus_clk = clk ;
518-
519510 /* set chip select to use */
520511 ctrl |= MX51_ECSPI_CTRL_CS (spi -> chip_select );
521512
522- if (spi_imx -> slave_mode && is_imx53_ecspi (spi_imx ))
523- ctrl |= (spi_imx -> slave_burst * 8 - 1 )
524- << MX51_ECSPI_CTRL_BL_OFFSET ;
513+ /*
514+ * The ctrl register must be written first, with the EN bit set other
515+ * registers must not be written to.
516+ */
517+ writel (ctrl , spi_imx -> base + MX51_ECSPI_CTRL );
518+
519+ testreg = readl (spi_imx -> base + MX51_ECSPI_TESTREG );
520+ if (spi -> mode & SPI_LOOP )
521+ testreg |= MX51_ECSPI_TESTREG_LBC ;
525522 else
526- ctrl |= ( spi_imx -> bits_per_word - 1 )
527- << MX51_ECSPI_CTRL_BL_OFFSET ;
523+ testreg &= ~ MX51_ECSPI_TESTREG_LBC ;
524+ writel ( testreg , spi_imx -> base + MX51_ECSPI_TESTREG ) ;
528525
529526 /*
530527 * eCSPI burst completion by Chip Select signal in Slave mode
@@ -548,25 +545,42 @@ static int mx51_ecspi_config(struct spi_device *spi)
548545 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL (spi -> chip_select );
549546 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL (spi -> chip_select );
550547 }
548+
551549 if (spi -> mode & SPI_CS_HIGH )
552550 cfg |= MX51_ECSPI_CONFIG_SSBPOL (spi -> chip_select );
553551 else
554552 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL (spi -> chip_select );
555553
556- if (spi_imx -> usedma )
557- ctrl |= MX51_ECSPI_CTRL_SMC ;
554+ writel (cfg , spi_imx -> base + MX51_ECSPI_CONFIG );
558555
559- /* CTRL register always go first to bring out controller from reset */
560- writel ( ctrl , spi_imx -> base + MX51_ECSPI_CTRL );
556+ return 0 ;
557+ }
561558
562- reg = readl (spi_imx -> base + MX51_ECSPI_TESTREG );
563- if (spi -> mode & SPI_LOOP )
564- reg |= MX51_ECSPI_TESTREG_LBC ;
559+ static int mx51_ecspi_config (struct spi_device * spi )
560+ {
561+ struct spi_imx_data * spi_imx = spi_master_get_devdata (spi -> master );
562+ u32 ctrl = readl (spi_imx -> base + MX51_ECSPI_CTRL );
563+ u32 clk = spi_imx -> speed_hz , delay ;
564+
565+ /* Clear BL field and set the right value */
566+ ctrl &= ~MX51_ECSPI_CTRL_BL_MASK ;
567+ if (spi_imx -> slave_mode && is_imx53_ecspi (spi_imx ))
568+ ctrl |= (spi_imx -> slave_burst * 8 - 1 )
569+ << MX51_ECSPI_CTRL_BL_OFFSET ;
565570 else
566- reg &= ~ MX51_ECSPI_TESTREG_LBC ;
567- writel ( reg , spi_imx -> base + MX51_ECSPI_TESTREG ) ;
571+ ctrl |= ( spi_imx -> bits_per_word - 1 )
572+ << MX51_ECSPI_CTRL_BL_OFFSET ;
568573
569- writel (cfg , spi_imx -> base + MX51_ECSPI_CONFIG );
574+ /* set clock speed */
575+ ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
576+ 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET );
577+ ctrl |= mx51_ecspi_clkdiv (spi_imx , spi_imx -> speed_hz , & clk );
578+ spi_imx -> spi_bus_clk = clk ;
579+
580+ if (spi_imx -> usedma )
581+ ctrl |= MX51_ECSPI_CTRL_SMC ;
582+
583+ writel (ctrl , spi_imx -> base + MX51_ECSPI_CTRL );
570584
571585 /*
572586 * Wait until the changes in the configuration register CONFIGREG
@@ -594,7 +608,6 @@ static void mx51_setup_wml(struct spi_imx_data *spi_imx)
594608 * Configure the DMA register: setup the watermark
595609 * and enable DMA request.
596610 */
597-
598611 writel (MX51_ECSPI_DMA_RX_WML (spi_imx -> wml - 1 ) |
599612 MX51_ECSPI_DMA_TX_WML (spi_imx -> wml ) |
600613 MX51_ECSPI_DMA_RXT_WML (spi_imx -> wml ) |
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