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Russell Kingdavem330
Russell King
authored and
davem330
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net: dsa: mv88e6xxx: combine port_set_speed and port_set_duplex
Setting the speed independently of duplex makes little sense; the two parameters result from negotiation or fixed setup, and may have inter- dependencies. Moreover, they are always controlled via the same register - having them split means we have to read-modify-write this register twice. Combine the two operations into a single port_set_speed_duplex() operation. Not only is this more efficient, it reduces the size of the code as well. Signed-off-by: Russell King <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/dsa/mv88e6xxx/chip.c‎

Lines changed: 33 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -452,8 +452,9 @@ static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452452
if (err)
453453
return err;
454454

455-
if (chip->info->ops->port_set_speed) {
456-
err = chip->info->ops->port_set_speed(chip, port, speed);
455+
if (chip->info->ops->port_set_speed_duplex) {
456+
err = chip->info->ops->port_set_speed_duplex(chip, port,
457+
speed, duplex);
457458
if (err && err != -EOPNOTSUPP)
458459
goto restore_link;
459460
}
@@ -467,12 +468,6 @@ static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
467468
goto restore_link;
468469
}
469470

470-
if (chip->info->ops->port_set_duplex) {
471-
err = chip->info->ops->port_set_duplex(chip, port, duplex);
472-
if (err && err != -EOPNOTSUPP)
473-
goto restore_link;
474-
}
475-
476471
err = mv88e6xxx_port_config_interface(chip, port, mode);
477472
restore_link:
478473
if (chip->info->ops->port_set_link(chip, port, link))
@@ -762,14 +757,9 @@ static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
762757
if (err)
763758
goto error;
764759

765-
if (ops->port_set_speed) {
766-
err = ops->port_set_speed(chip, port, speed);
767-
if (err && err != -EOPNOTSUPP)
768-
goto error;
769-
}
770-
771-
if (ops->port_set_duplex) {
772-
err = ops->port_set_duplex(chip, port, duplex);
760+
if (ops->port_set_speed_duplex) {
761+
err = ops->port_set_speed_duplex(chip, port,
762+
speed, duplex);
773763
if (err && err != -EOPNOTSUPP)
774764
goto error;
775765
}
@@ -3412,8 +3402,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
34123402
.phy_read = mv88e6185_phy_ppu_read,
34133403
.phy_write = mv88e6185_phy_ppu_write,
34143404
.port_set_link = mv88e6xxx_port_set_link,
3415-
.port_set_duplex = mv88e6xxx_port_set_duplex,
3416-
.port_set_speed = mv88e6185_port_set_speed,
3405+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
34173406
.port_tag_remap = mv88e6095_port_tag_remap,
34183407
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
34193408
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3452,8 +3441,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {
34523441
.phy_read = mv88e6185_phy_ppu_read,
34533442
.phy_write = mv88e6185_phy_ppu_write,
34543443
.port_set_link = mv88e6xxx_port_set_link,
3455-
.port_set_duplex = mv88e6xxx_port_set_duplex,
3456-
.port_set_speed = mv88e6185_port_set_speed,
3444+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
34573445
.port_set_frame_mode = mv88e6085_port_set_frame_mode,
34583446
.port_set_egress_floods = mv88e6185_port_set_egress_floods,
34593447
.port_set_upstream_port = mv88e6095_port_set_upstream_port,
@@ -3483,8 +3471,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
34833471
.phy_read = mv88e6xxx_g2_smi_phy_read,
34843472
.phy_write = mv88e6xxx_g2_smi_phy_write,
34853473
.port_set_link = mv88e6xxx_port_set_link,
3486-
.port_set_duplex = mv88e6xxx_port_set_duplex,
3487-
.port_set_speed = mv88e6185_port_set_speed,
3474+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
34883475
.port_tag_remap = mv88e6095_port_tag_remap,
34893476
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
34903477
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3523,8 +3510,7 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
35233510
.phy_read = mv88e6xxx_g2_smi_phy_read,
35243511
.phy_write = mv88e6xxx_g2_smi_phy_write,
35253512
.port_set_link = mv88e6xxx_port_set_link,
3526-
.port_set_duplex = mv88e6xxx_port_set_duplex,
3527-
.port_set_speed = mv88e6185_port_set_speed,
3513+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
35283514
.port_set_frame_mode = mv88e6085_port_set_frame_mode,
35293515
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
35303516
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -3558,8 +3544,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
35583544
.phy_read = mv88e6185_phy_ppu_read,
35593545
.phy_write = mv88e6185_phy_ppu_write,
35603546
.port_set_link = mv88e6xxx_port_set_link,
3561-
.port_set_duplex = mv88e6xxx_port_set_duplex,
3562-
.port_set_speed = mv88e6185_port_set_speed,
3547+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
35633548
.port_tag_remap = mv88e6095_port_tag_remap,
35643549
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
35653550
.port_set_egress_floods = mv88e6185_port_set_egress_floods,
@@ -3601,9 +3586,8 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
36013586
.phy_read = mv88e6xxx_g2_smi_phy_read,
36023587
.phy_write = mv88e6xxx_g2_smi_phy_write,
36033588
.port_set_link = mv88e6xxx_port_set_link,
3604-
.port_set_duplex = mv88e6xxx_port_set_duplex,
36053589
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3606-
.port_set_speed = mv88e6341_port_set_speed,
3590+
.port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
36073591
.port_max_speed_mode = mv88e6341_port_max_speed_mode,
36083592
.port_tag_remap = mv88e6095_port_tag_remap,
36093593
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
@@ -3654,8 +3638,7 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
36543638
.phy_read = mv88e6xxx_g2_smi_phy_read,
36553639
.phy_write = mv88e6xxx_g2_smi_phy_write,
36563640
.port_set_link = mv88e6xxx_port_set_link,
3657-
.port_set_duplex = mv88e6xxx_port_set_duplex,
3658-
.port_set_speed = mv88e6185_port_set_speed,
3641+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
36593642
.port_tag_remap = mv88e6095_port_tag_remap,
36603643
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
36613644
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3697,8 +3680,7 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {
36973680
.phy_read = mv88e6165_phy_read,
36983681
.phy_write = mv88e6165_phy_write,
36993682
.port_set_link = mv88e6xxx_port_set_link,
3700-
.port_set_duplex = mv88e6xxx_port_set_duplex,
3701-
.port_set_speed = mv88e6185_port_set_speed,
3683+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
37023684
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
37033685
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
37043686
.port_link_state = mv88e6352_port_link_state,
@@ -3733,9 +3715,8 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
37333715
.phy_read = mv88e6xxx_g2_smi_phy_read,
37343716
.phy_write = mv88e6xxx_g2_smi_phy_write,
37353717
.port_set_link = mv88e6xxx_port_set_link,
3736-
.port_set_duplex = mv88e6xxx_port_set_duplex,
37373718
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3738-
.port_set_speed = mv88e6185_port_set_speed,
3719+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
37393720
.port_tag_remap = mv88e6095_port_tag_remap,
37403721
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
37413722
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3777,9 +3758,8 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
37773758
.phy_read = mv88e6xxx_g2_smi_phy_read,
37783759
.phy_write = mv88e6xxx_g2_smi_phy_write,
37793760
.port_set_link = mv88e6xxx_port_set_link,
3780-
.port_set_duplex = mv88e6xxx_port_set_duplex,
37813761
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3782-
.port_set_speed = mv88e6352_port_set_speed,
3762+
.port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
37833763
.port_tag_remap = mv88e6095_port_tag_remap,
37843764
.port_set_policy = mv88e6352_port_set_policy,
37853765
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
@@ -3830,9 +3810,8 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
38303810
.phy_read = mv88e6xxx_g2_smi_phy_read,
38313811
.phy_write = mv88e6xxx_g2_smi_phy_write,
38323812
.port_set_link = mv88e6xxx_port_set_link,
3833-
.port_set_duplex = mv88e6xxx_port_set_duplex,
38343813
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3835-
.port_set_speed = mv88e6185_port_set_speed,
3814+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
38363815
.port_tag_remap = mv88e6095_port_tag_remap,
38373816
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
38383817
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3874,9 +3853,8 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
38743853
.phy_read = mv88e6xxx_g2_smi_phy_read,
38753854
.phy_write = mv88e6xxx_g2_smi_phy_write,
38763855
.port_set_link = mv88e6xxx_port_set_link,
3877-
.port_set_duplex = mv88e6xxx_port_set_duplex,
38783856
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3879-
.port_set_speed = mv88e6352_port_set_speed,
3857+
.port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
38803858
.port_tag_remap = mv88e6095_port_tag_remap,
38813859
.port_set_policy = mv88e6352_port_set_policy,
38823860
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
@@ -3929,8 +3907,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
39293907
.phy_read = mv88e6185_phy_ppu_read,
39303908
.phy_write = mv88e6185_phy_ppu_write,
39313909
.port_set_link = mv88e6xxx_port_set_link,
3932-
.port_set_duplex = mv88e6xxx_port_set_duplex,
3933-
.port_set_speed = mv88e6185_port_set_speed,
3910+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
39343911
.port_set_frame_mode = mv88e6085_port_set_frame_mode,
39353912
.port_set_egress_floods = mv88e6185_port_set_egress_floods,
39363913
.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
@@ -3967,9 +3944,8 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
39673944
.phy_read = mv88e6xxx_g2_smi_phy_read,
39683945
.phy_write = mv88e6xxx_g2_smi_phy_write,
39693946
.port_set_link = mv88e6xxx_port_set_link,
3970-
.port_set_duplex = mv88e6xxx_port_set_duplex,
39713947
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3972-
.port_set_speed = mv88e6390_port_set_speed,
3948+
.port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
39733949
.port_max_speed_mode = mv88e6390_port_max_speed_mode,
39743950
.port_tag_remap = mv88e6390_port_tag_remap,
39753951
.port_set_policy = mv88e6352_port_set_policy,
@@ -4028,9 +4004,8 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
40284004
.phy_read = mv88e6xxx_g2_smi_phy_read,
40294005
.phy_write = mv88e6xxx_g2_smi_phy_write,
40304006
.port_set_link = mv88e6xxx_port_set_link,
4031-
.port_set_duplex = mv88e6xxx_port_set_duplex,
40324007
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4033-
.port_set_speed = mv88e6390x_port_set_speed,
4008+
.port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
40344009
.port_max_speed_mode = mv88e6390x_port_max_speed_mode,
40354010
.port_tag_remap = mv88e6390_port_tag_remap,
40364011
.port_set_policy = mv88e6352_port_set_policy,
@@ -4089,9 +4064,8 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
40894064
.phy_read = mv88e6xxx_g2_smi_phy_read,
40904065
.phy_write = mv88e6xxx_g2_smi_phy_write,
40914066
.port_set_link = mv88e6xxx_port_set_link,
4092-
.port_set_duplex = mv88e6xxx_port_set_duplex,
40934067
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4094-
.port_set_speed = mv88e6390_port_set_speed,
4068+
.port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
40954069
.port_max_speed_mode = mv88e6390_port_max_speed_mode,
40964070
.port_tag_remap = mv88e6390_port_tag_remap,
40974071
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
@@ -4151,9 +4125,8 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
41514125
.phy_read = mv88e6xxx_g2_smi_phy_read,
41524126
.phy_write = mv88e6xxx_g2_smi_phy_write,
41534127
.port_set_link = mv88e6xxx_port_set_link,
4154-
.port_set_duplex = mv88e6xxx_port_set_duplex,
41554128
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4156-
.port_set_speed = mv88e6352_port_set_speed,
4129+
.port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
41574130
.port_tag_remap = mv88e6095_port_tag_remap,
41584131
.port_set_policy = mv88e6352_port_set_policy,
41594132
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
@@ -4211,9 +4184,8 @@ static const struct mv88e6xxx_ops mv88e6250_ops = {
42114184
.phy_read = mv88e6xxx_g2_smi_phy_read,
42124185
.phy_write = mv88e6xxx_g2_smi_phy_write,
42134186
.port_set_link = mv88e6xxx_port_set_link,
4214-
.port_set_duplex = mv88e6xxx_port_set_duplex,
42154187
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4216-
.port_set_speed = mv88e6250_port_set_speed,
4188+
.port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
42174189
.port_tag_remap = mv88e6095_port_tag_remap,
42184190
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
42194191
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -4250,9 +4222,8 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
42504222
.phy_read = mv88e6xxx_g2_smi_phy_read,
42514223
.phy_write = mv88e6xxx_g2_smi_phy_write,
42524224
.port_set_link = mv88e6xxx_port_set_link,
4253-
.port_set_duplex = mv88e6xxx_port_set_duplex,
42544225
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4255-
.port_set_speed = mv88e6390_port_set_speed,
4226+
.port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
42564227
.port_max_speed_mode = mv88e6390_port_max_speed_mode,
42574228
.port_tag_remap = mv88e6390_port_tag_remap,
42584229
.port_set_policy = mv88e6352_port_set_policy,
@@ -4314,8 +4285,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
43144285
.phy_read = mv88e6xxx_g2_smi_phy_read,
43154286
.phy_write = mv88e6xxx_g2_smi_phy_write,
43164287
.port_set_link = mv88e6xxx_port_set_link,
4317-
.port_set_duplex = mv88e6xxx_port_set_duplex,
4318-
.port_set_speed = mv88e6185_port_set_speed,
4288+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
43194289
.port_tag_remap = mv88e6095_port_tag_remap,
43204290
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
43214291
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -4358,8 +4328,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
43584328
.phy_read = mv88e6xxx_g2_smi_phy_read,
43594329
.phy_write = mv88e6xxx_g2_smi_phy_write,
43604330
.port_set_link = mv88e6xxx_port_set_link,
4361-
.port_set_duplex = mv88e6xxx_port_set_duplex,
4362-
.port_set_speed = mv88e6185_port_set_speed,
4331+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
43634332
.port_tag_remap = mv88e6095_port_tag_remap,
43644333
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
43654334
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -4400,9 +4369,8 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
44004369
.phy_read = mv88e6xxx_g2_smi_phy_read,
44014370
.phy_write = mv88e6xxx_g2_smi_phy_write,
44024371
.port_set_link = mv88e6xxx_port_set_link,
4403-
.port_set_duplex = mv88e6xxx_port_set_duplex,
44044372
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4405-
.port_set_speed = mv88e6341_port_set_speed,
4373+
.port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
44064374
.port_max_speed_mode = mv88e6341_port_max_speed_mode,
44074375
.port_tag_remap = mv88e6095_port_tag_remap,
44084376
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
@@ -4455,9 +4423,8 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
44554423
.phy_read = mv88e6xxx_g2_smi_phy_read,
44564424
.phy_write = mv88e6xxx_g2_smi_phy_write,
44574425
.port_set_link = mv88e6xxx_port_set_link,
4458-
.port_set_duplex = mv88e6xxx_port_set_duplex,
44594426
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4460-
.port_set_speed = mv88e6185_port_set_speed,
4427+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
44614428
.port_tag_remap = mv88e6095_port_tag_remap,
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.port_set_frame_mode = mv88e6351_port_set_frame_mode,
44634430
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -4497,9 +4464,8 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
44974464
.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
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.port_set_link = mv88e6xxx_port_set_link,
4500-
.port_set_duplex = mv88e6xxx_port_set_duplex,
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.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4502-
.port_set_speed = mv88e6185_port_set_speed,
4468+
.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
45034469
.port_tag_remap = mv88e6095_port_tag_remap,
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.port_set_frame_mode = mv88e6351_port_set_frame_mode,
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.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -4543,9 +4509,8 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
45434509
.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
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.port_set_link = mv88e6xxx_port_set_link,
4546-
.port_set_duplex = mv88e6xxx_port_set_duplex,
45474512
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4548-
.port_set_speed = mv88e6352_port_set_speed,
4513+
.port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
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.port_tag_remap = mv88e6095_port_tag_remap,
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.port_set_policy = mv88e6352_port_set_policy,
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.port_set_frame_mode = mv88e6351_port_set_frame_mode,
@@ -4605,9 +4570,8 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
46054570
.phy_read = mv88e6xxx_g2_smi_phy_read,
46064571
.phy_write = mv88e6xxx_g2_smi_phy_write,
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.port_set_link = mv88e6xxx_port_set_link,
4608-
.port_set_duplex = mv88e6xxx_port_set_duplex,
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.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4610-
.port_set_speed = mv88e6390_port_set_speed,
4574+
.port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
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.port_max_speed_mode = mv88e6390_port_max_speed_mode,
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.port_tag_remap = mv88e6390_port_tag_remap,
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.port_set_policy = mv88e6352_port_set_policy,
@@ -4670,9 +4634,8 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
46704634
.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
46724636
.port_set_link = mv88e6xxx_port_set_link,
4673-
.port_set_duplex = mv88e6xxx_port_set_duplex,
46744637
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4675-
.port_set_speed = mv88e6390x_port_set_speed,
4638+
.port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
46764639
.port_max_speed_mode = mv88e6390x_port_max_speed_mode,
46774640
.port_tag_remap = mv88e6390_port_tag_remap,
46784641
.port_set_policy = mv88e6352_port_set_policy,

‎drivers/net/dsa/mv88e6xxx/chip.h‎

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -399,15 +399,6 @@ struct mv88e6xxx_ops {
399399
*/
400400
int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
401401

402-
#define DUPLEX_UNFORCED -2
403-
404-
/* Port's MAC duplex mode
405-
*
406-
* Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
407-
* or DUPLEX_UNFORCED for normal duplex detection.
408-
*/
409-
int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
410-
411402
#define PAUSE_ON 1
412403
#define PAUSE_OFF 0
413404

@@ -417,13 +408,18 @@ struct mv88e6xxx_ops {
417408

418409
#define SPEED_MAX INT_MAX
419410
#define SPEED_UNFORCED -2
411+
#define DUPLEX_UNFORCED -2
420412

421-
/* Port's MAC speed (in Mbps)
413+
/* Port's MAC speed (in Mbps) and MAC duplex mode
422414
*
423415
* Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
424416
* Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
417+
*
418+
* Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
419+
* or DUPLEX_UNFORCED for normal duplex detection.
425420
*/
426-
int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
421+
int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
422+
int speed, int duplex);
427423

428424
/* What interface mode should be used for maximum speed? */
429425
phy_interface_t (*port_max_speed_mode)(int port);

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