@@ -11,7 +11,7 @@ The RISC-V supervisor ISA manual specifies three interrupt sources that are
1111attached to every HLIC: software interrupts, the timer interrupt, and external
1212interrupts. Software interrupts are used to send IPIs between cores. The
1313timer interrupt comes from an architecturally mandated real-time timer that is
14- controller via Supervisor Binary Interface (SBI) calls and CSR reads. External
14+ controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
1515interrupts connect all other device interrupts to the HLIC, which are routed
1616via the platform-level interrupt controller (PLIC).
1717
@@ -25,7 +25,15 @@ in the system.
2525
2626Required properties:
2727- compatible : "riscv,cpu-intc"
28- - #interrupt-cells : should be <1>
28+ - #interrupt-cells : should be <1>. The interrupt sources are defined by the
29+ RISC-V supervisor ISA manual, with only the following three interrupts being
30+ defined for supervisor mode:
31+ - Source 1 is the supervisor software interrupt, which can be sent by an SBI
32+ call and is reserved for use by software.
33+ - Source 5 is the supervisor timer interrupt, which can be configured by
34+ SBI calls and implements a one-shot timer.
35+ - Source 9 is the supervisor external interrupt, which chains to all other
36+ device interrupts.
2937- interrupt-controller : Identifies the node as an interrupt controller
3038
3139Furthermore, this interrupt-controller MUST be embedded inside the cpu
@@ -38,7 +46,7 @@ An example device tree entry for a HLIC is show below.
3846 ...
3947 cpu1-intc: interrupt-controller {
4048 #interrupt-cells = <1>;
41- compatible = "riscv, cpu-intc", "sifive,fu540-c000- cpu-intc";
49+ compatible = "sifive,fu540-c000- cpu-intc", "riscv, cpu-intc";
4250 interrupt-controller;
4351 };
4452 };
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