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396 | 396 | #define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */
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397 | 397 | #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
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398 | 398 |
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399 |
| -#define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ |
400 |
| -#define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ |
401 |
| -#define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ |
402 |
| - |
403 |
| -#define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */ |
| 399 | +/* Mask for RX packet buffer size */ |
| 400 | +#define IGC_RXPBSIZE_EXP_MASK GENMASK(5, 0) |
| 401 | +#define IGC_BMC2OSPBSIZE_MASK GENMASK(11, 6) |
| 402 | +#define IGC_RXPBSIZE_BE_MASK GENMASK(17, 12) |
| 403 | +/* Mask for timestamp in RX buffer */ |
| 404 | +#define IGC_RXPBS_CFG_TS_EN_MASK GENMASK(31, 31) |
| 405 | +/* High-priority RX packet buffer size (KB). Used for Express traffic when preemption is enabled */ |
| 406 | +#define IGC_RXPBSIZE_EXP(x) FIELD_PREP(IGC_RXPBSIZE_EXP_MASK, (x)) |
| 407 | +/* BMC to OS packet buffer size in KB */ |
| 408 | +#define IGC_BMC2OSPBSIZE(x) FIELD_PREP(IGC_BMC2OSPBSIZE_MASK, (x)) |
| 409 | +/* Low-priority RX packet buffer size (KB). Used for BE traffic when preemption is enabled */ |
| 410 | +#define IGC_RXPBSIZE_BE(x) FIELD_PREP(IGC_RXPBSIZE_BE_MASK, (x)) |
| 411 | +/* Enable RX packet buffer for timestamp descriptor, saving 16 bytes per packet if set */ |
| 412 | +#define IGC_RXPBS_CFG_TS_EN FIELD_PREP(IGC_RXPBS_CFG_TS_EN_MASK, 1) |
| 413 | +/* Default value following I225/I226 SW User Manual Section 8.3.1 */ |
| 414 | +#define IGC_RXPBSIZE_EXP_BMC_DEFAULT ( \ |
| 415 | + IGC_RXPBSIZE_EXP(34) | IGC_BMC2OSPBSIZE(2)) |
| 416 | +#define IGC_RXPBSIZE_EXP_BMC_BE_TSN ( \ |
| 417 | + IGC_RXPBSIZE_EXP(15) | IGC_BMC2OSPBSIZE(2) | IGC_RXPBSIZE_BE(15)) |
| 418 | + |
| 419 | +/* Mask for TX packet buffer size */ |
| 420 | +#define IGC_TXPB0SIZE_MASK GENMASK(5, 0) |
| 421 | +#define IGC_TXPB1SIZE_MASK GENMASK(11, 6) |
| 422 | +#define IGC_TXPB2SIZE_MASK GENMASK(17, 12) |
| 423 | +#define IGC_TXPB3SIZE_MASK GENMASK(23, 18) |
| 424 | +/* Mask for OS to BMC packet buffer size */ |
| 425 | +#define IGC_OS2BMCPBSIZE_MASK GENMASK(29, 24) |
| 426 | +/* TX Packet buffer size in KB */ |
| 427 | +#define IGC_TXPB0SIZE(x) FIELD_PREP(IGC_TXPB0SIZE_MASK, (x)) |
| 428 | +#define IGC_TXPB1SIZE(x) FIELD_PREP(IGC_TXPB1SIZE_MASK, (x)) |
| 429 | +#define IGC_TXPB2SIZE(x) FIELD_PREP(IGC_TXPB2SIZE_MASK, (x)) |
| 430 | +#define IGC_TXPB3SIZE(x) FIELD_PREP(IGC_TXPB3SIZE_MASK, (x)) |
| 431 | +/* OS to BMC packet buffer size in KB */ |
| 432 | +#define IGC_OS2BMCPBSIZE(x) FIELD_PREP(IGC_OS2BMCPBSIZE_MASK, (x)) |
| 433 | +/* Default value following I225/I226 SW User Manual Section 8.3.2 */ |
| 434 | +#define IGC_TXPBSIZE_DEFAULT ( \ |
| 435 | + IGC_TXPB0SIZE(20) | IGC_TXPB1SIZE(0) | IGC_TXPB2SIZE(0) | \ |
| 436 | + IGC_TXPB3SIZE(0) | IGC_OS2BMCPBSIZE(4)) |
| 437 | +#define IGC_TXPBSIZE_TSN ( \ |
| 438 | + IGC_TXPB0SIZE(7) | IGC_TXPB1SIZE(7) | IGC_TXPB2SIZE(7) | \ |
| 439 | + IGC_TXPB3SIZE(7) | IGC_OS2BMCPBSIZE(4)) |
404 | 440 |
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405 | 441 | #define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */
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406 | 442 | #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */
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574 | 610 | #define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x3f) << 2)
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575 | 611 | #define IGC_PTM_CTRL_PTM_TO(usec) (((usec) & 0xff) << 8)
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576 | 612 |
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577 |
| -#define IGC_PTM_SHORT_CYC_DEFAULT 1 /* Default short cycle interval */ |
| 613 | +/* A short cycle time of 1us theoretically should work, but appears to be too |
| 614 | + * short in practice. |
| 615 | + */ |
| 616 | +#define IGC_PTM_SHORT_CYC_DEFAULT 4 /* Default short cycle interval */ |
578 | 617 | #define IGC_PTM_CYC_TIME_DEFAULT 5 /* Default PTM cycle time */
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579 | 618 | #define IGC_PTM_TIMEOUT_DEFAULT 255 /* Default timeout for PTM errors */
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580 | 619 |
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593 | 632 | #define IGC_PTM_STAT_T4M1_OVFL BIT(3) /* T4 minus T1 overflow */
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594 | 633 | #define IGC_PTM_STAT_ADJUST_1ST BIT(4) /* 1588 timer adjusted during 1st PTM cycle */
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595 | 634 | #define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */
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| 635 | +#define IGC_PTM_STAT_ALL GENMASK(5, 0) /* Used to clear all status */ |
596 | 636 |
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597 | 637 | /* PCIe PTM Cycle Control */
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598 | 638 | #define IGC_PTM_CYCLE_CTRL_CYC_TIME(msec) ((msec) & 0x3ff) /* PTM Cycle Time (msec) */
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