3838/* Transmit operation: */
3939/* */
4040/* 0 byte transmit */
41- /* BUS: S A8 ACK P */
41+ /* BUS: S A8 ACK P(*) */
4242/* IRQ: DTE WAIT */
4343/* ICIC: */
4444/* ICCR: 0x94 0x90 */
4545/* ICDR: A8 */
4646/* */
4747/* 1 byte transmit */
48- /* BUS: S A8 ACK D8(1) ACK P */
48+ /* BUS: S A8 ACK D8(1) ACK P(*) */
4949/* IRQ: DTE WAIT WAIT */
5050/* ICIC: -DTE */
5151/* ICCR: 0x94 0x90 */
5252/* ICDR: A8 D8(1) */
5353/* */
5454/* 2 byte transmit */
55- /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */
55+ /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
5656/* IRQ: DTE WAIT WAIT WAIT */
5757/* ICIC: -DTE */
5858/* ICCR: 0x94 0x90 */
6666/* 0 byte receive - not supported since slave may hold SDA low */
6767/* */
6868/* 1 byte receive [TX] | [RX] */
69- /* BUS: S A8 ACK | D8(1) ACK P */
69+ /* BUS: S A8 ACK | D8(1) ACK P(*) */
7070/* IRQ: DTE WAIT | WAIT DTE */
7171/* ICIC: -DTE | +DTE */
7272/* ICCR: 0x94 0x81 | 0xc0 */
7373/* ICDR: A8 | D8(1) */
7474/* */
7575/* 2 byte receive [TX]| [RX] */
76- /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P */
76+ /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
7777/* IRQ: DTE WAIT | WAIT WAIT DTE */
7878/* ICIC: -DTE | +DTE */
7979/* ICCR: 0x94 0x81 | 0xc0 */
8080/* ICDR: A8 | D8(1) D8(2) */
8181/* */
82- /* 3 byte receive [TX] | [RX] */
82+ /* 3 byte receive [TX] | [RX] (*) */
8383/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
8484/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
8585/* ICIC: -DTE | +DTE */
9494/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
9595/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
9696/* */
97- /* S D7 D6 D5 D4 D3 D2 D1 D0 P */
97+ /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
9898/* ___ */
9999/* WAIT IRQ ________________________________/ \___________ */
100100/* TACK IRQ ____________________________________/ \_______ */
103103/* _______________________________________________ */
104104/* BUSY __/ \_ */
105105/* */
106+ /* (*) The STOP condition is only sent by the master at the end of the last */
107+ /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
108+ /* only cleared after the STOP condition, so, between messages we have to */
109+ /* poll for the DTE bit. */
110+ /* */
106111
107112enum sh_mobile_i2c_op {
108113 OP_START = 0 ,
@@ -132,6 +137,7 @@ struct sh_mobile_i2c_data {
132137 struct i2c_msg * msg ;
133138 int pos ;
134139 int sr ;
140+ bool send_stop ;
135141};
136142
137143#define IIC_FLAG_HAS_ICIC67 (1 << 0)
@@ -322,7 +328,7 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
322328 break ;
323329 case OP_TX_STOP : /* write data and issue a stop afterwards */
324330 iic_wr (pd , ICDR , data );
325- iic_wr (pd , ICCR , 0x90 );
331+ iic_wr (pd , ICCR , pd -> send_stop ? 0x90 : 0x94 );
326332 break ;
327333 case OP_TX_TO_RX : /* select read mode */
328334 iic_wr (pd , ICCR , 0x81 );
@@ -469,22 +475,25 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
469475 return IRQ_HANDLED ;
470476}
471477
472- static int start_ch (struct sh_mobile_i2c_data * pd , struct i2c_msg * usr_msg )
478+ static int start_ch (struct sh_mobile_i2c_data * pd , struct i2c_msg * usr_msg ,
479+ bool do_init )
473480{
474481 if (usr_msg -> len == 0 && (usr_msg -> flags & I2C_M_RD )) {
475482 dev_err (pd -> dev , "Unsupported zero length i2c read\n" );
476483 return - EIO ;
477484 }
478485
479- /* Initialize channel registers */
480- iic_set_clr (pd , ICCR , 0 , ICCR_ICE );
486+ if (do_init ) {
487+ /* Initialize channel registers */
488+ iic_set_clr (pd , ICCR , 0 , ICCR_ICE );
481489
482- /* Enable channel and configure rx ack */
483- iic_set_clr (pd , ICCR , ICCR_ICE , 0 );
490+ /* Enable channel and configure rx ack */
491+ iic_set_clr (pd , ICCR , ICCR_ICE , 0 );
484492
485- /* Set the clock */
486- iic_wr (pd , ICCL , pd -> iccl & 0xff );
487- iic_wr (pd , ICCH , pd -> icch & 0xff );
493+ /* Set the clock */
494+ iic_wr (pd , ICCL , pd -> iccl & 0xff );
495+ iic_wr (pd , ICCH , pd -> icch & 0xff );
496+ }
488497
489498 pd -> msg = usr_msg ;
490499 pd -> pos = -1 ;
@@ -495,6 +504,30 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
495504 return 0 ;
496505}
497506
507+ static int poll_dte (struct sh_mobile_i2c_data * pd )
508+ {
509+ int i ;
510+
511+ for (i = 1000 ; i ; i -- ) {
512+ u_int8_t val = iic_rd (pd , ICSR );
513+
514+ if (val & ICSR_DTE )
515+ break ;
516+
517+ if (val & ICSR_TACK )
518+ return - EIO ;
519+
520+ udelay (10 );
521+ }
522+
523+ if (!i ) {
524+ dev_warn (pd -> dev , "Timeout polling for DTE!\n" );
525+ return - ETIMEDOUT ;
526+ }
527+
528+ return 0 ;
529+ }
530+
498531static int poll_busy (struct sh_mobile_i2c_data * pd )
499532{
500533 int i ;
@@ -539,13 +572,16 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
539572
540573 /* Process all messages */
541574 for (i = 0 ; i < num ; i ++ ) {
575+ bool do_start = pd -> send_stop || !i ;
542576 msg = & msgs [i ];
577+ pd -> send_stop = i == num - 1 || msg -> flags & I2C_M_STOP ;
543578
544- err = start_ch (pd , msg );
579+ err = start_ch (pd , msg , do_start );
545580 if (err )
546581 break ;
547582
548- i2c_op (pd , OP_START , 0 );
583+ if (do_start )
584+ i2c_op (pd , OP_START , 0 );
549585
550586 /* The interrupt handler takes care of the rest... */
551587 k = wait_event_timeout (pd -> wait ,
@@ -557,7 +593,10 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
557593 break ;
558594 }
559595
560- err = poll_busy (pd );
596+ if (pd -> send_stop )
597+ err = poll_busy (pd );
598+ else
599+ err = poll_dte (pd );
561600 if (err < 0 )
562601 break ;
563602 }
@@ -571,7 +610,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
571610
572611static u32 sh_mobile_i2c_func (struct i2c_adapter * adapter )
573612{
574- return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL ;
613+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING ;
575614}
576615
577616static struct i2c_algorithm sh_mobile_i2c_algorithm = {
0 commit comments