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Nitin Rawatvinodkoul
Nitin Rawat
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vinodkoul
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phy: qcom-qmp-ufs: Add PHY and PLL regulator load
Add phy and pll regulator load voting support for all supported platforms by introducing dedicated regulator bulk data arrays with their load values. This ensures stable operation and proper power management for these platforms where regulators are shared between the QMP UFS PHY and other IP blocks by setting appropriate regulator load currents during PHY operations. Signed-off-by: Nitin Rawat <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/qualcomm/phy-qcom-qmp-ufs.c‎

Lines changed: 104 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1164,10 +1164,80 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
11641164
readl(base + offset);
11651165
}
11661166

1167-
/* Default regulator bulk data (no load used) */
1168-
static const struct regulator_bulk_data qmp_phy_vreg_l[] = {
1169-
{ .supply = "vdda-phy" },
1170-
{ .supply = "vdda-pll" },
1167+
/* Regulator bulk data with load values for specific configurations */
1168+
static const struct regulator_bulk_data msm8996_ufsphy_vreg_l[] = {
1169+
{ .supply = "vdda-phy", .init_load_uA = 51400 },
1170+
{ .supply = "vdda-pll", .init_load_uA = 14600 },
1171+
};
1172+
1173+
static const struct regulator_bulk_data sa8775p_ufsphy_vreg_l[] = {
1174+
{ .supply = "vdda-phy", .init_load_uA = 137000 },
1175+
{ .supply = "vdda-pll", .init_load_uA = 18300 },
1176+
};
1177+
1178+
static const struct regulator_bulk_data sc7280_ufsphy_vreg_l[] = {
1179+
{ .supply = "vdda-phy", .init_load_uA = 97500 },
1180+
{ .supply = "vdda-pll", .init_load_uA = 18400 },
1181+
};
1182+
1183+
static const struct regulator_bulk_data sc8280xp_ufsphy_vreg_l[] = {
1184+
{ .supply = "vdda-phy", .init_load_uA = 85700 },
1185+
{ .supply = "vdda-pll", .init_load_uA = 18300 },
1186+
};
1187+
1188+
static const struct regulator_bulk_data sdm845_ufsphy_vreg_l[] = {
1189+
{ .supply = "vdda-phy", .init_load_uA = 51400 },
1190+
{ .supply = "vdda-pll", .init_load_uA = 14600 },
1191+
};
1192+
1193+
static const struct regulator_bulk_data sm6115_ufsphy_vreg_l[] = {
1194+
{ .supply = "vdda-phy", .init_load_uA = 51400 },
1195+
{ .supply = "vdda-pll", .init_load_uA = 14200 },
1196+
};
1197+
1198+
static const struct regulator_bulk_data sm7150_ufsphy_vreg_l[] = {
1199+
{ .supply = "vdda-phy", .init_load_uA = 62900 },
1200+
{ .supply = "vdda-pll", .init_load_uA = 18300 },
1201+
};
1202+
1203+
static const struct regulator_bulk_data sm8150_ufsphy_vreg_l[] = {
1204+
{ .supply = "vdda-phy", .init_load_uA = 90200 },
1205+
{ .supply = "vdda-pll", .init_load_uA = 19000 },
1206+
};
1207+
1208+
static const struct regulator_bulk_data sm8250_ufsphy_vreg_l[] = {
1209+
{ .supply = "vdda-phy", .init_load_uA = 89900 },
1210+
{ .supply = "vdda-pll", .init_load_uA = 18800 },
1211+
};
1212+
1213+
static const struct regulator_bulk_data sm8350_ufsphy_vreg_l[] = {
1214+
{ .supply = "vdda-phy", .init_load_uA = 91600 },
1215+
{ .supply = "vdda-pll", .init_load_uA = 19000 },
1216+
};
1217+
1218+
static const struct regulator_bulk_data sm8450_ufsphy_vreg_l[] = {
1219+
{ .supply = "vdda-phy", .init_load_uA = 173000 },
1220+
{ .supply = "vdda-pll", .init_load_uA = 24900 },
1221+
};
1222+
1223+
static const struct regulator_bulk_data sm8475_ufsphy_vreg_l[] = {
1224+
{ .supply = "vdda-phy", .init_load_uA = 213030 },
1225+
{ .supply = "vdda-pll", .init_load_uA = 18340 },
1226+
};
1227+
1228+
static const struct regulator_bulk_data sm8550_ufsphy_vreg_l[] = {
1229+
{ .supply = "vdda-phy", .init_load_uA = 188000 },
1230+
{ .supply = "vdda-pll", .init_load_uA = 18300 },
1231+
};
1232+
1233+
static const struct regulator_bulk_data sm8650_ufsphy_vreg_l[] = {
1234+
{ .supply = "vdda-phy", .init_load_uA = 205000 },
1235+
{ .supply = "vdda-pll", .init_load_uA = 17500 },
1236+
};
1237+
1238+
static const struct regulator_bulk_data sm8750_ufsphy_vreg_l[] = {
1239+
{ .supply = "vdda-phy", .init_load_uA = 213000 },
1240+
{ .supply = "vdda-pll", .init_load_uA = 18300 },
11711241
};
11721242

11731243
static const struct qmp_ufs_offsets qmp_ufs_offsets = {
@@ -1203,8 +1273,8 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
12031273
.rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
12041274
},
12051275

1206-
.vreg_list = qmp_phy_vreg_l,
1207-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1276+
.vreg_list = msm8996_ufsphy_vreg_l,
1277+
.num_vregs = ARRAY_SIZE(msm8996_ufsphy_vreg_l),
12081278

12091279
.regs = ufsphy_v2_regs_layout,
12101280

@@ -1240,8 +1310,8 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
12401310
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
12411311
.max_gear = UFS_HS_G4,
12421312
},
1243-
.vreg_list = qmp_phy_vreg_l,
1244-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1313+
.vreg_list = sa8775p_ufsphy_vreg_l,
1314+
.num_vregs = ARRAY_SIZE(sa8775p_ufsphy_vreg_l),
12451315
.regs = ufsphy_v5_regs_layout,
12461316
};
12471317

@@ -1274,8 +1344,8 @@ static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
12741344
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
12751345
.max_gear = UFS_HS_G4,
12761346
},
1277-
.vreg_list = qmp_phy_vreg_l,
1278-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1347+
.vreg_list = sc7280_ufsphy_vreg_l,
1348+
.num_vregs = ARRAY_SIZE(sc7280_ufsphy_vreg_l),
12791349
.regs = ufsphy_v4_regs_layout,
12801350
};
12811351

@@ -1308,8 +1378,8 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
13081378
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
13091379
.max_gear = UFS_HS_G4,
13101380
},
1311-
.vreg_list = qmp_phy_vreg_l,
1312-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1381+
.vreg_list = sc8280xp_ufsphy_vreg_l,
1382+
.num_vregs = ARRAY_SIZE(sc8280xp_ufsphy_vreg_l),
13131383
.regs = ufsphy_v5_regs_layout,
13141384
};
13151385

@@ -1333,8 +1403,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
13331403
.serdes = sdm845_ufsphy_hs_b_serdes,
13341404
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
13351405
},
1336-
.vreg_list = qmp_phy_vreg_l,
1337-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1406+
.vreg_list = sdm845_ufsphy_vreg_l,
1407+
.num_vregs = ARRAY_SIZE(sdm845_ufsphy_vreg_l),
13381408
.regs = ufsphy_v3_regs_layout,
13391409

13401410
.no_pcs_sw_reset = true,
@@ -1360,8 +1430,8 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
13601430
.serdes = sm6115_ufsphy_hs_b_serdes,
13611431
.serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
13621432
},
1363-
.vreg_list = qmp_phy_vreg_l,
1364-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1433+
.vreg_list = sm6115_ufsphy_vreg_l,
1434+
.num_vregs = ARRAY_SIZE(sm6115_ufsphy_vreg_l),
13651435
.regs = ufsphy_v2_regs_layout,
13661436

13671437
.no_pcs_sw_reset = true,
@@ -1387,8 +1457,8 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
13871457
.serdes = sdm845_ufsphy_hs_b_serdes,
13881458
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
13891459
},
1390-
.vreg_list = qmp_phy_vreg_l,
1391-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1460+
.vreg_list = sm7150_ufsphy_vreg_l,
1461+
.num_vregs = ARRAY_SIZE(sm7150_ufsphy_vreg_l),
13921462
.regs = ufsphy_v3_regs_layout,
13931463

13941464
.no_pcs_sw_reset = true,
@@ -1423,8 +1493,8 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
14231493
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
14241494
.max_gear = UFS_HS_G4,
14251495
},
1426-
.vreg_list = qmp_phy_vreg_l,
1427-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1496+
.vreg_list = sm8150_ufsphy_vreg_l,
1497+
.num_vregs = ARRAY_SIZE(sm8150_ufsphy_vreg_l),
14281498
.regs = ufsphy_v4_regs_layout,
14291499
};
14301500

@@ -1457,8 +1527,8 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
14571527
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
14581528
.max_gear = UFS_HS_G4,
14591529
},
1460-
.vreg_list = qmp_phy_vreg_l,
1461-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1530+
.vreg_list = sm8250_ufsphy_vreg_l,
1531+
.num_vregs = ARRAY_SIZE(sm8250_ufsphy_vreg_l),
14621532
.regs = ufsphy_v4_regs_layout,
14631533
};
14641534

@@ -1491,8 +1561,8 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
14911561
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
14921562
.max_gear = UFS_HS_G4,
14931563
},
1494-
.vreg_list = qmp_phy_vreg_l,
1495-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1564+
.vreg_list = sm8350_ufsphy_vreg_l,
1565+
.num_vregs = ARRAY_SIZE(sm8350_ufsphy_vreg_l),
14961566
.regs = ufsphy_v5_regs_layout,
14971567
};
14981568

@@ -1525,8 +1595,8 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
15251595
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
15261596
.max_gear = UFS_HS_G4,
15271597
},
1528-
.vreg_list = qmp_phy_vreg_l,
1529-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1598+
.vreg_list = sm8450_ufsphy_vreg_l,
1599+
.num_vregs = ARRAY_SIZE(sm8450_ufsphy_vreg_l),
15301600
.regs = ufsphy_v5_regs_layout,
15311601
};
15321602

@@ -1561,8 +1631,8 @@ static const struct qmp_phy_cfg sm8475_ufsphy_cfg = {
15611631
.pcs_num = ARRAY_SIZE(sm8475_ufsphy_g4_pcs),
15621632
.max_gear = UFS_HS_G4,
15631633
},
1564-
.vreg_list = qmp_phy_vreg_l,
1565-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1634+
.vreg_list = sm8475_ufsphy_vreg_l,
1635+
.num_vregs = ARRAY_SIZE(sm8475_ufsphy_vreg_l),
15661636
.regs = ufsphy_v6_regs_layout,
15671637
};
15681638

@@ -1606,8 +1676,8 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
16061676
.pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
16071677
.max_gear = UFS_HS_G5,
16081678
},
1609-
.vreg_list = qmp_phy_vreg_l,
1610-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1679+
.vreg_list = sm8550_ufsphy_vreg_l,
1680+
.num_vregs = ARRAY_SIZE(sm8550_ufsphy_vreg_l),
16111681
.regs = ufsphy_v6_regs_layout,
16121682
};
16131683

@@ -1638,8 +1708,8 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
16381708
.max_gear = UFS_HS_G5,
16391709
},
16401710

1641-
.vreg_list = qmp_phy_vreg_l,
1642-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1711+
.vreg_list = sm8650_ufsphy_vreg_l,
1712+
.num_vregs = ARRAY_SIZE(sm8650_ufsphy_vreg_l),
16431713
.regs = ufsphy_v6_regs_layout,
16441714
};
16451715

@@ -1676,8 +1746,8 @@ static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
16761746
.max_gear = UFS_HS_G5,
16771747
},
16781748

1679-
.vreg_list = qmp_phy_vreg_l,
1680-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1749+
.vreg_list = sm8750_ufsphy_vreg_l,
1750+
.num_vregs = ARRAY_SIZE(sm8750_ufsphy_vreg_l),
16811751
.regs = ufsphy_v6_regs_layout,
16821752

16831753
};

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