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xavierhwdledford
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RDMA/hns: Initialize the PCI device for hip08 RoCE
The hip08 RoCE engine is a PCI device. This patch mainly obtains some information of PCI device for hip08 RoCE from hns3 NIC driver in the initialization. Signed-off-by: Lijun Ou <[email protected]> Signed-off-by: Shaobo Xu <[email protected]> Signed-off-by: Wei Hu (Xavier) <[email protected]> Signed-off-by: Doug Ledford <[email protected]>
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drivers/infiniband/hw/hns/Kconfig

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@@ -19,3 +19,13 @@ config INFINIBAND_HNS_HIP06
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To compile this driver as a module, choose M here: the module
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will be called hns-roce-hw-v1.
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config INFINIBAND_HNS_HIP08
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tristate "Hisilicon Hip08 Family RoCE support"
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depends on INFINIBAND_HNS && PCI && HNS3
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---help---
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RoCE driver support for Hisilicon RoCE engine in Hisilicon Hip08 SoC.
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The RoCE engine is a PCI device.
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To compile this driver as a module, choose M here: the module
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will be called hns-roce-hw-v2.

drivers/infiniband/hw/hns/Makefile

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# Makefile for the Hisilicon RoCE drivers.
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#
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ccflags-y := -Idrivers/net/ethernet/hisilicon/hns3
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obj-$(CONFIG_INFINIBAND_HNS) += hns-roce.o
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hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_eq.o hns_roce_pd.o \
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hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \
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hns_roce_cq.o hns_roce_alloc.o
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obj-$(CONFIG_INFINIBAND_HNS_HIP06) += hns-roce-hw-v1.o
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hns-roce-hw-v1-objs := hns_roce_hw_v1.o
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obj-$(CONFIG_INFINIBAND_HNS_HIP08) += hns-roce-hw-v2.o
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hns-roce-hw-v2-objs := hns_roce_hw_v2.o

drivers/infiniband/hw/hns/hns_roce_device.h

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@@ -540,6 +540,8 @@ struct hns_roce_hw {
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struct hns_roce_dev {
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struct ib_device ib_dev;
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struct platform_device *pdev;
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struct pci_dev *pci_dev;
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struct device *dev;
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struct hns_roce_uar priv_uar;
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const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
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spinlock_t sm_lock;
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/*
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* Copyright (c) 2016-2017 Hisilicon Limited.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/acpi.h>
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#include <linux/etherdevice.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <rdma/ib_umem.h>
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#include "hnae3.h"
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#include "hns_roce_common.h"
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#include "hns_roce_device.h"
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#include "hns_roce_cmd.h"
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#include "hns_roce_hem.h"
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static const struct hns_roce_hw hns_roce_hw_v2;
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static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
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/* required last entry */
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{0, }
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};
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static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
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struct hnae3_handle *handle)
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{
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const struct pci_device_id *id;
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id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
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if (!id) {
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dev_err(hr_dev->dev, "device is not compatible!\n");
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return -ENXIO;
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}
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hr_dev->hw = &hns_roce_hw_v2;
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/* Get info from NIC driver. */
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hr_dev->reg_base = handle->rinfo.roce_io_base;
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hr_dev->caps.num_ports = 1;
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hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
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hr_dev->iboe.phy_port[0] = 0;
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/* cmd issue mode: 0 is poll, 1 is event */
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hr_dev->cmd_mod = 0;
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hr_dev->loop_idc = 0;
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return 0;
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}
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static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
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{
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struct hns_roce_dev *hr_dev;
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int ret;
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hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
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if (!hr_dev)
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return -ENOMEM;
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hr_dev->pci_dev = handle->pdev;
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hr_dev->dev = &handle->pdev->dev;
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handle->priv = hr_dev;
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ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
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if (ret) {
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dev_err(hr_dev->dev, "Get Configuration failed!\n");
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goto error_failed_get_cfg;
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}
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ret = hns_roce_init(hr_dev);
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if (ret) {
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dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
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goto error_failed_get_cfg;
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}
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return 0;
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error_failed_get_cfg:
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ib_dealloc_device(&hr_dev->ib_dev);
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return ret;
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}
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static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
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bool reset)
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{
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struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
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hns_roce_exit(hr_dev);
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ib_dealloc_device(&hr_dev->ib_dev);
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}
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static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
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.init_instance = hns_roce_hw_v2_init_instance,
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.uninit_instance = hns_roce_hw_v2_uninit_instance,
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};
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static struct hnae3_client hns_roce_hw_v2_client = {
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.name = "hns_roce_hw_v2",
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.type = HNAE3_CLIENT_ROCE,
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.ops = &hns_roce_hw_v2_ops,
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};
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static int __init hns_roce_hw_v2_init(void)
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{
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return hnae3_register_client(&hns_roce_hw_v2_client);
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}
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static void __exit hns_roce_hw_v2_exit(void)
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{
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hnae3_unregister_client(&hns_roce_hw_v2_client);
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}
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module_init(hns_roce_hw_v2_init);
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module_exit(hns_roce_hw_v2_exit);
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_AUTHOR("Wei Hu <[email protected]>");
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MODULE_AUTHOR("Lijun Ou <[email protected]>");
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MODULE_AUTHOR("Shaobo Xu <[email protected]>");
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MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");

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