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airliedairlied
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Merge tag 'amd-drm-fixes-5.6-2020-03-11' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
amd-drm-fixes-5.6-2020-03-11: amdgpu: - Update the display watermark bounding box for navi14 - Fix fetching vbios directly from rom on vega20/arcturus - Navi and renoir watermark fixes Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents e3c3b6e + 1d2686d commit d944326

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-15
lines changed

5 files changed

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lines changed

‎drivers/gpu/drm/amd/amdgpu/soc15.c‎

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,13 @@
8989
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
9090
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
9191
#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
92+
93+
/* for Vega20/arcturus regiter offset change */
94+
#define mmROM_INDEX_VG20 0x00e4
95+
#define mmROM_INDEX_VG20_BASE_IDX 0
96+
#define mmROM_DATA_VG20 0x00e5
97+
#define mmROM_DATA_VG20_BASE_IDX 0
98+
9299
/*
93100
* Indirect registers accessor
94101
*/
@@ -309,6 +316,8 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
309316
{
310317
u32 *dw_ptr;
311318
u32 i, length_dw;
319+
uint32_t rom_index_offset;
320+
uint32_t rom_data_offset;
312321

313322
if (bios == NULL)
314323
return false;
@@ -321,11 +330,23 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
321330
dw_ptr = (u32 *)bios;
322331
length_dw = ALIGN(length_bytes, 4) / 4;
323332

333+
switch (adev->asic_type) {
334+
case CHIP_VEGA20:
335+
case CHIP_ARCTURUS:
336+
rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
337+
rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
338+
break;
339+
default:
340+
rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
341+
rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
342+
break;
343+
}
344+
324345
/* set rom index to 0 */
325-
WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
346+
WREG32(rom_index_offset, 0);
326347
/* read out the rom data */
327348
for (i = 0; i < length_dw; i++)
328-
dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
349+
dw_ptr[i] = RREG32(rom_data_offset);
329350

330351
return true;
331352
}

‎drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c‎

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -335,6 +335,117 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
335335
.use_urgent_burst_bw = 0
336336
};
337337

338+
struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
339+
.clock_limits = {
340+
{
341+
.state = 0,
342+
.dcfclk_mhz = 560.0,
343+
.fabricclk_mhz = 560.0,
344+
.dispclk_mhz = 513.0,
345+
.dppclk_mhz = 513.0,
346+
.phyclk_mhz = 540.0,
347+
.socclk_mhz = 560.0,
348+
.dscclk_mhz = 171.0,
349+
.dram_speed_mts = 8960.0,
350+
},
351+
{
352+
.state = 1,
353+
.dcfclk_mhz = 694.0,
354+
.fabricclk_mhz = 694.0,
355+
.dispclk_mhz = 642.0,
356+
.dppclk_mhz = 642.0,
357+
.phyclk_mhz = 600.0,
358+
.socclk_mhz = 694.0,
359+
.dscclk_mhz = 214.0,
360+
.dram_speed_mts = 11104.0,
361+
},
362+
{
363+
.state = 2,
364+
.dcfclk_mhz = 875.0,
365+
.fabricclk_mhz = 875.0,
366+
.dispclk_mhz = 734.0,
367+
.dppclk_mhz = 734.0,
368+
.phyclk_mhz = 810.0,
369+
.socclk_mhz = 875.0,
370+
.dscclk_mhz = 245.0,
371+
.dram_speed_mts = 14000.0,
372+
},
373+
{
374+
.state = 3,
375+
.dcfclk_mhz = 1000.0,
376+
.fabricclk_mhz = 1000.0,
377+
.dispclk_mhz = 1100.0,
378+
.dppclk_mhz = 1100.0,
379+
.phyclk_mhz = 810.0,
380+
.socclk_mhz = 1000.0,
381+
.dscclk_mhz = 367.0,
382+
.dram_speed_mts = 16000.0,
383+
},
384+
{
385+
.state = 4,
386+
.dcfclk_mhz = 1200.0,
387+
.fabricclk_mhz = 1200.0,
388+
.dispclk_mhz = 1284.0,
389+
.dppclk_mhz = 1284.0,
390+
.phyclk_mhz = 810.0,
391+
.socclk_mhz = 1200.0,
392+
.dscclk_mhz = 428.0,
393+
.dram_speed_mts = 16000.0,
394+
},
395+
/*Extra state, no dispclk ramping*/
396+
{
397+
.state = 5,
398+
.dcfclk_mhz = 1200.0,
399+
.fabricclk_mhz = 1200.0,
400+
.dispclk_mhz = 1284.0,
401+
.dppclk_mhz = 1284.0,
402+
.phyclk_mhz = 810.0,
403+
.socclk_mhz = 1200.0,
404+
.dscclk_mhz = 428.0,
405+
.dram_speed_mts = 16000.0,
406+
},
407+
},
408+
.num_states = 5,
409+
.sr_exit_time_us = 8.6,
410+
.sr_enter_plus_exit_time_us = 10.9,
411+
.urgent_latency_us = 4.0,
412+
.urgent_latency_pixel_data_only_us = 4.0,
413+
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
414+
.urgent_latency_vm_data_only_us = 4.0,
415+
.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
416+
.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
417+
.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
418+
.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
419+
.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
420+
.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
421+
.max_avg_sdp_bw_use_normal_percent = 40.0,
422+
.max_avg_dram_bw_use_normal_percent = 40.0,
423+
.writeback_latency_us = 12.0,
424+
.ideal_dram_bw_after_urgent_percent = 40.0,
425+
.max_request_size_bytes = 256,
426+
.dram_channel_width_bytes = 2,
427+
.fabric_datapath_to_dcn_data_return_bytes = 64,
428+
.dcn_downspread_percent = 0.5,
429+
.downspread_percent = 0.38,
430+
.dram_page_open_time_ns = 50.0,
431+
.dram_rw_turnaround_time_ns = 17.5,
432+
.dram_return_buffer_per_channel_bytes = 8192,
433+
.round_trip_ping_latency_dcfclk_cycles = 131,
434+
.urgent_out_of_order_return_per_channel_bytes = 256,
435+
.channel_interleave_bytes = 256,
436+
.num_banks = 8,
437+
.num_chans = 8,
438+
.vmm_page_size_bytes = 4096,
439+
.dram_clock_change_latency_us = 404.0,
440+
.dummy_pstate_latency_us = 5.0,
441+
.writeback_dram_clock_change_latency_us = 23.0,
442+
.return_bus_width_bytes = 64,
443+
.dispclk_dppclk_vco_speed_mhz = 3850,
444+
.xfc_bus_transport_time_us = 20,
445+
.xfc_xbuf_latency_tolerance_us = 4,
446+
.use_urgent_burst_bw = 0
447+
};
448+
338449
struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
339450

340451
#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
@@ -3291,6 +3402,9 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st
32913402
static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
32923403
uint32_t hw_internal_rev)
32933404
{
3405+
if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3406+
return &dcn2_0_nv14_soc;
3407+
32943408
if (ASICREV_IS_NAVI12_P(hw_internal_rev))
32953409
return &dcn2_0_nv12_soc;
32963410

‎drivers/gpu/drm/amd/powerplay/amdgpu_smu.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2006,8 +2006,11 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
20062006
smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
20072007
smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
20082008
smu_set_watermarks_table(smu, table, clock_ranges);
2009-
smu->watermarks_bitmap |= WATERMARKS_EXIST;
2010-
smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
2009+
2010+
if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
2011+
smu->watermarks_bitmap |= WATERMARKS_EXIST;
2012+
smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
2013+
}
20112014
}
20122015

20132016
mutex_unlock(&smu->mutex);

‎drivers/gpu/drm/amd/powerplay/navi10_ppt.c‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1062,15 +1062,6 @@ static int navi10_display_config_changed(struct smu_context *smu)
10621062
{
10631063
int ret = 0;
10641064

1065-
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1066-
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1067-
ret = smu_write_watermarks_table(smu);
1068-
if (ret)
1069-
return ret;
1070-
1071-
smu->watermarks_bitmap |= WATERMARKS_LOADED;
1072-
}
1073-
10741065
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
10751066
smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
10761067
smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
@@ -1493,6 +1484,7 @@ static int navi10_set_watermarks_table(struct smu_context *smu,
14931484
*clock_ranges)
14941485
{
14951486
int i;
1487+
int ret = 0;
14961488
Watermarks_t *table = watermarks;
14971489

14981490
if (!table || !clock_ranges)
@@ -1544,6 +1536,18 @@ static int navi10_set_watermarks_table(struct smu_context *smu,
15441536
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
15451537
}
15461538

1539+
smu->watermarks_bitmap |= WATERMARKS_EXIST;
1540+
1541+
/* pass data to smu controller */
1542+
if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1543+
ret = smu_write_watermarks_table(smu);
1544+
if (ret) {
1545+
pr_err("Failed to update WMTABLE!");
1546+
return ret;
1547+
}
1548+
smu->watermarks_bitmap |= WATERMARKS_LOADED;
1549+
}
1550+
15471551
return 0;
15481552
}
15491553

‎drivers/gpu/drm/amd/powerplay/renoir_ppt.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -806,9 +806,10 @@ static int renoir_set_watermarks_table(
806806
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
807807
}
808808

809+
smu->watermarks_bitmap |= WATERMARKS_EXIST;
810+
809811
/* pass data to smu controller */
810-
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
811-
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
812+
if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
812813
ret = smu_write_watermarks_table(smu);
813814
if (ret) {
814815
pr_err("Failed to update WMTABLE!");

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