@@ -2602,6 +2602,7 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
26022602 return - ENOENT ;
26032603
26042604 for_each_child_of_node (node , port_np ) {
2605+ phy_interface_t phy_if ;
26052606 struct am65_cpsw_port * port ;
26062607 u32 port_id ;
26072608
@@ -2667,14 +2668,36 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
26672668
26682669 /* get phy/link info */
26692670 port -> slave .port_np = of_node_get (port_np );
2670- ret = of_get_phy_mode (port_np , & port -> slave . phy_if );
2671+ ret = of_get_phy_mode (port_np , & phy_if );
26712672 if (ret ) {
26722673 dev_err (dev , "%pOF read phy-mode err %d\n" ,
26732674 port_np , ret );
26742675 goto of_node_put ;
26752676 }
26762677
2677- ret = phy_set_mode_ext (port -> slave .ifphy , PHY_MODE_ETHERNET , port -> slave .phy_if );
2678+ /* CPSW controllers supported by this driver have a fixed
2679+ * internal TX delay in RGMII mode. Fix up PHY mode to account
2680+ * for this and warn about Device Trees that claim to have a TX
2681+ * delay on the PCB.
2682+ */
2683+ switch (phy_if ) {
2684+ case PHY_INTERFACE_MODE_RGMII_ID :
2685+ phy_if = PHY_INTERFACE_MODE_RGMII_RXID ;
2686+ break ;
2687+ case PHY_INTERFACE_MODE_RGMII_TXID :
2688+ phy_if = PHY_INTERFACE_MODE_RGMII ;
2689+ break ;
2690+ case PHY_INTERFACE_MODE_RGMII :
2691+ case PHY_INTERFACE_MODE_RGMII_RXID :
2692+ dev_warn (dev ,
2693+ "RGMII mode without internal TX delay unsupported; please fix your Device Tree\n" );
2694+ break ;
2695+ default :
2696+ break ;
2697+ }
2698+
2699+ port -> slave .phy_if = phy_if ;
2700+ ret = phy_set_mode_ext (port -> slave .ifphy , PHY_MODE_ETHERNET , phy_if );
26782701 if (ret )
26792702 goto of_node_put ;
26802703
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