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Desnes Nunes
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phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300
JIRA: https://issues.redhat.com/browse/RHEL-122019 commit ebf198f Author: Ziyue Zhang <[email protected]> Date: Mon, 10 Mar 2025 14:30:57 +0800 The PCIe Gen4x2 PHY for qcs8300 has a lot of difference with sa8775p. So the qcs8300_qmp_gen4x2_pcie_rx_alt_tbl for qcs8300 is added. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Ziyue Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]> Signed-off-by: Desnes Nunes <[email protected]>
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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c‎

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Original file line numberDiff line numberDiff line change
@@ -805,6 +805,58 @@ static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] = {
805805
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
806806
};
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808+
static const struct qmp_phy_init_tbl qcs8300_qmp_gen4x2_pcie_rx_alt_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
810+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
820+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
840+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
841+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
842+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
843+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
844+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
845+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
846+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
847+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
848+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
849+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
850+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
851+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
852+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
853+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
854+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
855+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
856+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
857+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
858+
};
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808860
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
809861
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
810862
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -3343,6 +3395,40 @@ static const struct qmp_phy_cfg qcs615_pciephy_cfg = {
33433395
.phy_status = PHYSTATUS,
33443396
};
33453397

3398+
static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = {
3399+
.lanes = 2,
3400+
.offsets = &qmp_pcie_offsets_v5_20,
3401+
3402+
.tbls = {
3403+
.serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
3404+
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
3405+
.tx = sa8775p_qmp_gen4_pcie_tx_tbl,
3406+
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
3407+
.rx = qcs8300_qmp_gen4x2_pcie_rx_alt_tbl,
3408+
.rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl),
3409+
.pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
3410+
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
3411+
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
3412+
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
3413+
},
3414+
3415+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3416+
.serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
3417+
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
3418+
.pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
3419+
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
3420+
},
3421+
3422+
.reset_list = sdm845_pciephy_reset_l,
3423+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3424+
.vreg_list = qmp_phy_vreg_l,
3425+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3426+
.regs = pciephy_v5_regs_layout,
3427+
3428+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3429+
.phy_status = PHYSTATUS_4_20,
3430+
};
3431+
33463432
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
33473433
.lanes = 1,
33483434

@@ -4944,6 +5030,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
49445030
}, {
49455031
.compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
49465032
.data = &qcs615_pciephy_cfg,
5033+
}, {
5034+
.compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy",
5035+
.data = &qcs8300_qmp_gen4x2_pciephy_cfg,
49475036
}, {
49485037
.compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
49495038
.data = &sa8775p_qmp_gen4x2_pciephy_cfg,

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