@@ -2852,6 +2852,32 @@ static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2852
2852
RTL_R32 (tp , CSIDR ) : ~0 ;
2853
2853
}
2854
2854
2855
+ static void rtl_disable_zrxdc_timeout (struct rtl8169_private * tp )
2856
+ {
2857
+ struct pci_dev * pdev = tp -> pci_dev ;
2858
+ u32 csi ;
2859
+ int rc ;
2860
+ u8 val ;
2861
+
2862
+ #define RTL_GEN3_RELATED_OFF 0x0890
2863
+ #define RTL_GEN3_ZRXDC_NONCOMPL 0x1
2864
+ if (pdev -> cfg_size > RTL_GEN3_RELATED_OFF ) {
2865
+ rc = pci_read_config_byte (pdev , RTL_GEN3_RELATED_OFF , & val );
2866
+ if (rc == PCIBIOS_SUCCESSFUL ) {
2867
+ val &= ~RTL_GEN3_ZRXDC_NONCOMPL ;
2868
+ rc = pci_write_config_byte (pdev , RTL_GEN3_RELATED_OFF ,
2869
+ val );
2870
+ if (rc == PCIBIOS_SUCCESSFUL )
2871
+ return ;
2872
+ }
2873
+ }
2874
+
2875
+ netdev_notice_once (tp -> dev ,
2876
+ "No native access to PCI extended config space, falling back to CSI\n" );
2877
+ csi = rtl_csi_read (tp , RTL_GEN3_RELATED_OFF );
2878
+ rtl_csi_write (tp , RTL_GEN3_RELATED_OFF , csi & ~RTL_GEN3_ZRXDC_NONCOMPL );
2879
+ }
2880
+
2855
2881
static void rtl_set_aspm_entry_latency (struct rtl8169_private * tp , u8 val )
2856
2882
{
2857
2883
struct pci_dev * pdev = tp -> pci_dev ;
@@ -3824,6 +3850,7 @@ static void rtl_hw_start_8125d(struct rtl8169_private *tp)
3824
3850
3825
3851
static void rtl_hw_start_8126a (struct rtl8169_private * tp )
3826
3852
{
3853
+ rtl_disable_zrxdc_timeout (tp );
3827
3854
rtl_set_def_aspm_entry_latency (tp );
3828
3855
rtl_hw_start_8125_common (tp );
3829
3856
}
0 commit comments