@@ -745,14 +745,6 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
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amdgpu_ring_write (ring , PACKETJ (0 , 0 , 0 , PACKETJ_TYPE6 ));
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amdgpu_ring_write (ring , 0 );
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- amdgpu_ring_write (ring , PACKETJ (regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET ,
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- 0 , 0 , PACKETJ_TYPE0 ));
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- amdgpu_ring_write (ring , 0x3fbc );
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-
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- amdgpu_ring_write (ring , PACKETJ (JRBC_DEC_EXTERNAL_REG_WRITE_ADDR ,
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- 0 , 0 , PACKETJ_TYPE0 ));
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- amdgpu_ring_write (ring , 0x1 );
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-
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amdgpu_ring_write (ring , PACKETJ (0 , 0 , 0 , PACKETJ_TYPE6 ));
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amdgpu_ring_write (ring , 0 );
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@@ -1090,7 +1082,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
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SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
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SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
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8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */
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- 22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */
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+ 18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */
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8 + 16 ,
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.emit_ib_size = 22 , /* jpeg_v4_0_3_dec_ring_emit_ib */
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.emit_ib = jpeg_v4_0_3_dec_ring_emit_ib ,
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