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20 | 20 | #include <linux/pm_clock.h> |
21 | 21 | #include <linux/pm_domain.h> |
22 | 22 | #include <linux/slab.h> |
| 23 | +#include <linux/soc/renesas/r9a06g032-sysctrl.h> |
23 | 24 | #include <linux/spinlock.h> |
24 | 25 | #include <dt-bindings/clock/r9a06g032-sysctrl.h> |
25 | 26 |
|
| 27 | +#define R9A06G032_SYSCTRL_DMAMUX 0xA0 |
| 28 | + |
26 | 29 | struct r9a06g032_gate { |
27 | 30 | u16 gate, reset, ready, midle, |
28 | 31 | scon, mirack, mistat; |
@@ -315,6 +318,30 @@ struct r9a06g032_priv { |
315 | 318 | void __iomem *reg; |
316 | 319 | }; |
317 | 320 |
|
| 321 | +static struct r9a06g032_priv *sysctrl_priv; |
| 322 | + |
| 323 | +/* Exported helper to access the DMAMUX register */ |
| 324 | +int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) |
| 325 | +{ |
| 326 | + unsigned long flags; |
| 327 | + u32 dmamux; |
| 328 | + |
| 329 | + if (!sysctrl_priv) |
| 330 | + return -EPROBE_DEFER; |
| 331 | + |
| 332 | + spin_lock_irqsave(&sysctrl_priv->lock, flags); |
| 333 | + |
| 334 | + dmamux = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); |
| 335 | + dmamux &= ~mask; |
| 336 | + dmamux |= val & mask; |
| 337 | + writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); |
| 338 | + |
| 339 | + spin_unlock_irqrestore(&sysctrl_priv->lock, flags); |
| 340 | + |
| 341 | + return 0; |
| 342 | +} |
| 343 | +EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux); |
| 344 | + |
318 | 345 | /* register/bit pairs are encoded as an uint16_t */ |
319 | 346 | static void |
320 | 347 | clk_rdesc_set(struct r9a06g032_priv *clocks, |
@@ -963,7 +990,13 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) |
963 | 990 | if (error) |
964 | 991 | return error; |
965 | 992 |
|
966 | | - return r9a06g032_add_clk_domain(dev); |
| 993 | + error = r9a06g032_add_clk_domain(dev); |
| 994 | + if (error) |
| 995 | + return error; |
| 996 | + |
| 997 | + sysctrl_priv = clocks; |
| 998 | + |
| 999 | + return 0; |
967 | 1000 | } |
968 | 1001 |
|
969 | 1002 | static const struct of_device_id r9a06g032_match[] = { |
|
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