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octeon_ep: Add driver framework and device initialization
Add driver framework and device setup and initialization for Octeon PCI Endpoint NIC. Add implementation to load module, initilaize, register network device, cleanup and unload module. Signed-off-by: Veerasenareddy Burru <[email protected]> Signed-off-by: Abhijit Ayarekar <[email protected]> Signed-off-by: Satananda Burla <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎Documentation/networking/device_drivers/ethernet/index.rst

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@@ -39,6 +39,7 @@ Contents:
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intel/iavf
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intel/ice
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marvell/octeontx2
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marvell/octeon_ep
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mellanox/mlx5
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microsoft/netvsc
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neterion/s2io

‎Documentation/networking/device_drivers/ethernet/marvell/octeon_ep.rst

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.. SPDX-License-Identifier: GPL-2.0+
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====================================================================
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Linux kernel networking driver for Marvell's Octeon PCI Endpoint NIC
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====================================================================
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Network driver for Marvell's Octeon PCI EndPoint NIC.
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Copyright (c) 2020 Marvell International Ltd.
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Contents
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========
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- `Overview`_
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- `Supported Devices`_
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- `Interface Control`_
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Overview
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========
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This driver implements networking functionality of Marvell's Octeon PCI
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EndPoint NIC.
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Supported Devices
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=================
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Currently, this driver support following devices:
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* Network controller: Cavium, Inc. Device b200
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Interface Control
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=================
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Network Interface control like changing mtu, link speed, link down/up are
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done by writing command to mailbox command queue, a mailbox interface
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implemented through a reserved region in BAR4.
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This driver writes the commands into the mailbox and the firmware on the
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Octeon device processes them. The firmware also sends unsolicited notifications
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to driver for events suchs as link change, through notification queue
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implemented as part of mailbox interface.

‎MAINTAINERS

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F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
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F: drivers/mmc/host/sdhci-xenon*
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MARVELL OCTEON ENDPOINT DRIVER
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M: Veerasenareddy Burru <[email protected]>
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M: Abhijit Ayarekar <[email protected]>
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L: [email protected]
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S: Supported
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F: drivers/net/ethernet/marvell/octeon_ep
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MATROX FRAMEBUFFER DRIVER
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L: [email protected]
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S: Orphan

‎drivers/net/ethernet/marvell/Kconfig

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source "drivers/net/ethernet/marvell/octeontx2/Kconfig"
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source "drivers/net/ethernet/marvell/octeon_ep/Kconfig"
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source "drivers/net/ethernet/marvell/prestera/Kconfig"
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endif # NET_VENDOR_MARVELL

‎drivers/net/ethernet/marvell/Makefile

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@@ -11,5 +11,6 @@ obj-$(CONFIG_MVPP2) += mvpp2/
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obj-$(CONFIG_PXA168_ETH) += pxa168_eth.o
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obj-$(CONFIG_SKGE) += skge.o
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obj-$(CONFIG_SKY2) += sky2.o
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obj-y += octeon_ep/
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obj-y += octeontx2/
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obj-y += prestera/

‎drivers/net/ethernet/marvell/octeon_ep/Kconfig

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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Marvell's Octeon PCI Endpoint NIC Driver Configuration
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#
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config OCTEON_EP
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tristate "Marvell Octeon PCI Endpoint NIC Driver"
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depends on 64BIT
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depends on PCI
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depends on PTP_1588_CLOCK_OPTIONAL
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help
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This driver supports networking functionality of Marvell's
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Octeon PCI Endpoint NIC.
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To know the list of devices supported by this driver, refer
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documentation in
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<file:Documentation/networking/device_drivers/ethernet/marvell/octeon_ep.rst>.
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To compile this drivers as a module, choose M here. Name of the
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module is octeon_ep.

‎drivers/net/ethernet/marvell/octeon_ep/Makefile

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# SPDX-License-Identifier: GPL-2.0
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#
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# Network driver for Marvell's Octeon PCI Endpoint NIC
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#
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obj-$(CONFIG_OCTEON_EP) += octeon_ep.o
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octeon_ep-y := octep_main.o octep_cn9k_pf.o octep_tx.o octep_rx.o \
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octep_ctrl_mbox.o octep_ctrl_net.o

‎drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

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// SPDX-License-Identifier: GPL-2.0
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/* Marvell Octeon EP (EndPoint) Ethernet Driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include "octep_config.h"
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#include "octep_main.h"
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#include "octep_regs_cn9k_pf.h"
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/* Names of Hardware non-queue generic interrupts */
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static char *cn93_non_ioq_msix_names[] = {
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"epf_ire_rint",
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"epf_ore_rint",
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"epf_vfire_rint0",
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"epf_vfire_rint1",
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"epf_vfore_rint0",
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"epf_vfore_rint1",
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"epf_mbox_rint0",
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"epf_mbox_rint1",
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"epf_oei_rint",
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"epf_dma_rint",
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"epf_dma_vf_rint0",
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"epf_dma_vf_rint1",
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"epf_pp_vf_rint0",
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"epf_pp_vf_rint1",
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"epf_misc_rint",
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"epf_rsvd",
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};
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/* Reset all hardware Tx/Rx queues */
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static void octep_reset_io_queues_cn93_pf(struct octep_device *oct)
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{
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}
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/* Initialize windowed addresses to access some hardware registers */
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static void octep_setup_pci_window_regs_cn93_pf(struct octep_device *oct)
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{
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}
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/* Configure Hardware mapping: inform hardware which rings belong to PF. */
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static void octep_configure_ring_mapping_cn93_pf(struct octep_device *oct)
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{
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}
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/* Initialize configuration limits and initial active config 93xx PF. */
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static void octep_init_config_cn93_pf(struct octep_device *oct)
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{
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struct octep_config *conf = oct->conf;
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struct pci_dev *pdev = oct->pdev;
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u64 val;
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/* Read ring configuration:
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* PF ring count, number of VFs and rings per VF supported
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*/
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val = octep_read_csr64(oct, CN93_SDP_EPF_RINFO);
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conf->sriov_cfg.max_rings_per_vf = CN93_SDP_EPF_RINFO_RPVF(val);
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conf->sriov_cfg.active_rings_per_vf = conf->sriov_cfg.max_rings_per_vf;
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conf->sriov_cfg.max_vfs = CN93_SDP_EPF_RINFO_NVFS(val);
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conf->sriov_cfg.active_vfs = conf->sriov_cfg.max_vfs;
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conf->sriov_cfg.vf_srn = CN93_SDP_EPF_RINFO_SRN(val);
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val = octep_read_csr64(oct, CN93_SDP_MAC_PF_RING_CTL(oct->pcie_port));
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conf->pf_ring_cfg.srn = CN93_SDP_MAC_PF_RING_CTL_SRN(val);
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conf->pf_ring_cfg.max_io_rings = CN93_SDP_MAC_PF_RING_CTL_RPPF(val);
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conf->pf_ring_cfg.active_io_rings = conf->pf_ring_cfg.max_io_rings;
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dev_info(&pdev->dev, "pf_srn=%u rpvf=%u nvfs=%u rppf=%u\n",
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conf->pf_ring_cfg.srn, conf->sriov_cfg.active_rings_per_vf,
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conf->sriov_cfg.active_vfs, conf->pf_ring_cfg.active_io_rings);
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conf->iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS;
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conf->iq.instr_type = OCTEP_64BYTE_INSTR;
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conf->iq.pkind = 0;
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conf->iq.db_min = OCTEP_DB_MIN;
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conf->iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD;
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conf->oq.num_descs = OCTEP_OQ_MAX_DESCRIPTORS;
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conf->oq.buf_size = OCTEP_OQ_BUF_SIZE;
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conf->oq.refill_threshold = OCTEP_OQ_REFILL_THRESHOLD;
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conf->oq.oq_intr_pkt = OCTEP_OQ_INTR_PKT_THRESHOLD;
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conf->oq.oq_intr_time = OCTEP_OQ_INTR_TIME_THRESHOLD;
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conf->msix_cfg.non_ioq_msix = CN93_NUM_NON_IOQ_INTR;
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conf->msix_cfg.ioq_msix = conf->pf_ring_cfg.active_io_rings;
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conf->msix_cfg.non_ioq_msix_names = cn93_non_ioq_msix_names;
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conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr + (0x400000ull * 7);
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}
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/* Setup registers for a hardware Tx Queue */
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static void octep_setup_iq_regs_cn93_pf(struct octep_device *oct, int iq_no)
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{
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}
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/* Setup registers for a hardware Rx Queue */
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static void octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_no)
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{
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}
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/* Setup registers for a PF mailbox */
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static void octep_setup_mbox_regs_cn93_pf(struct octep_device *oct, int q_no)
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{
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}
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/* Interrupts handler for all non-queue generic interrupts. */
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static irqreturn_t octep_non_ioq_intr_handler_cn93_pf(void *dev)
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{
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return IRQ_HANDLED;
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}
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/* Tx/Rx queue interrupt handler */
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static irqreturn_t octep_ioq_intr_handler_cn93_pf(void *data)
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{
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return IRQ_HANDLED;
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}
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/* soft reset of 93xx */
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static int octep_soft_reset_cn93_pf(struct octep_device *oct)
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{
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dev_info(&oct->pdev->dev, "CN93XX: Doing soft reset\n");
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octep_write_csr64(oct, CN93_SDP_WIN_WR_MASK_REG, 0xFF);
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/* Set core domain reset bit */
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OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1S, 1);
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/* Wait for 100ms as Octeon resets. */
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mdelay(100);
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/* clear core domain reset bit */
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OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1C, 1);
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return 0;
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}
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/* Re-initialize Octeon hardware registers */
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static void octep_reinit_regs_cn93_pf(struct octep_device *oct)
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{
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}
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/* Enable all interrupts */
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static void octep_enable_interrupts_cn93_pf(struct octep_device *oct)
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{
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}
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/* Disable all interrupts */
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static void octep_disable_interrupts_cn93_pf(struct octep_device *oct)
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{
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}
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/* Get new Octeon Read Index: index of descriptor that Octeon reads next. */
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static u32 octep_update_iq_read_index_cn93_pf(struct octep_iq *iq)
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{
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return 0;
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}
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/* Enable a hardware Tx Queue */
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static void octep_enable_iq_cn93_pf(struct octep_device *oct, int iq_no)
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{
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}
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/* Enable a hardware Rx Queue */
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static void octep_enable_oq_cn93_pf(struct octep_device *oct, int oq_no)
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{
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}
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/* Enable all hardware Tx/Rx Queues assined to PF */
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static void octep_enable_io_queues_cn93_pf(struct octep_device *oct)
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{
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}
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/* Disable a hardware Tx Queue assined to PF */
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static void octep_disable_iq_cn93_pf(struct octep_device *oct, int iq_no)
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{
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}
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/* Disable a hardware Rx Queue assined to PF */
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static void octep_disable_oq_cn93_pf(struct octep_device *oct, int oq_no)
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{
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}
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/* Disable all hardware Tx/Rx Queues assined to PF */
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static void octep_disable_io_queues_cn93_pf(struct octep_device *oct)
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{
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}
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/* Dump hardware registers (including Tx/Rx queues) for debugging. */
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static void octep_dump_registers_cn93_pf(struct octep_device *oct)
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{
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}
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/**
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* octep_device_setup_cn93_pf() - Setup Octeon device.
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*
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* @oct: Octeon device private data structure.
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*
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* - initialize hardware operations.
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* - get target side pcie port number for the device.
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* - setup window access to hardware registers.
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* - set initial configuration and max limits.
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* - setup hardware mapping of rings to the PF device.
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*/
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void octep_device_setup_cn93_pf(struct octep_device *oct)
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{
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oct->hw_ops.setup_iq_regs = octep_setup_iq_regs_cn93_pf;
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oct->hw_ops.setup_oq_regs = octep_setup_oq_regs_cn93_pf;
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oct->hw_ops.setup_mbox_regs = octep_setup_mbox_regs_cn93_pf;
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oct->hw_ops.non_ioq_intr_handler = octep_non_ioq_intr_handler_cn93_pf;
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oct->hw_ops.ioq_intr_handler = octep_ioq_intr_handler_cn93_pf;
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oct->hw_ops.soft_reset = octep_soft_reset_cn93_pf;
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oct->hw_ops.reinit_regs = octep_reinit_regs_cn93_pf;
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oct->hw_ops.enable_interrupts = octep_enable_interrupts_cn93_pf;
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oct->hw_ops.disable_interrupts = octep_disable_interrupts_cn93_pf;
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oct->hw_ops.update_iq_read_idx = octep_update_iq_read_index_cn93_pf;
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oct->hw_ops.enable_iq = octep_enable_iq_cn93_pf;
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oct->hw_ops.enable_oq = octep_enable_oq_cn93_pf;
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oct->hw_ops.enable_io_queues = octep_enable_io_queues_cn93_pf;
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oct->hw_ops.disable_iq = octep_disable_iq_cn93_pf;
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oct->hw_ops.disable_oq = octep_disable_oq_cn93_pf;
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oct->hw_ops.disable_io_queues = octep_disable_io_queues_cn93_pf;
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oct->hw_ops.reset_io_queues = octep_reset_io_queues_cn93_pf;
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oct->hw_ops.dump_registers = octep_dump_registers_cn93_pf;
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octep_setup_pci_window_regs_cn93_pf(oct);
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oct->pcie_port = octep_read_csr64(oct, CN93_SDP_MAC_NUMBER) & 0xff;
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dev_info(&oct->pdev->dev,
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"Octeon device using PCIE Port %d\n", oct->pcie_port);
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octep_init_config_cn93_pf(oct);
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octep_configure_ring_mapping_cn93_pf(oct);
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}

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