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gregkhgregkh
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Merge 5.14-rc7 into usb-next
We need the USB fix in here as well. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2 parents e4788ed + e22ce8e commit 85fb1a2

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‎Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,10 +24,10 @@ allOf:
2424
select:
2525
properties:
2626
compatible:
27-
items:
28-
- enum:
29-
- sifive,fu540-c000-ccache
30-
- sifive,fu740-c000-ccache
27+
contains:
28+
enum:
29+
- sifive,fu540-c000-ccache
30+
- sifive,fu740-c000-ccache
3131

3232
required:
3333
- compatible

‎MAINTAINERS

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3866,6 +3866,16 @@ L: [email protected]
38663866
S: Maintained
38673867
F: drivers/mtd/nand/raw/brcmnand/
38683868

3869+
BROADCOM STB PCIE DRIVER
3870+
M: Jim Quinlan <[email protected]>
3871+
M: Nicolas Saenz Julienne <[email protected]>
3872+
M: Florian Fainelli <[email protected]>
3873+
M: [email protected]
3874+
L: [email protected]
3875+
S: Maintained
3876+
F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
3877+
F: drivers/pci/controller/pcie-brcmstb.c
3878+
38693879
BROADCOM SYSTEMPORT ETHERNET DRIVER
38703880
M: Florian Fainelli <[email protected]>
38713881
L: [email protected]
@@ -4498,7 +4508,7 @@ L: [email protected]
44984508
S: Supported
44994509
W: https://clangbuiltlinux.github.io/
45004510
B: https://github.com/ClangBuiltLinux/linux/issues
4501-
C: irc://chat.freenode.net/clangbuiltlinux
4511+
C: irc://irc.libera.chat/clangbuiltlinux
45024512
F: Documentation/kbuild/llvm.rst
45034513
F: include/linux/compiler-clang.h
45044514
F: scripts/clang-tools/
@@ -14430,6 +14440,13 @@ S: Maintained
1443014440
F: Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
1443114441
F: drivers/pci/controller/dwc/pcie-histb.c
1443214442

14443+
PCIE DRIVER FOR INTEL LGM GW SOC
14444+
M: Rahul Tanwar <[email protected]>
14445+
L: [email protected]
14446+
S: Maintained
14447+
F: Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
14448+
F: drivers/pci/controller/dwc/pcie-intel-gw.c
14449+
1443314450
PCIE DRIVER FOR MEDIATEK
1443414451
M: Ryder Lee <[email protected]>
1443514452
M: Jianjun Wang <[email protected]>

‎Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
VERSION = 5
33
PATCHLEVEL = 14
44
SUBLEVEL = 0
5-
EXTRAVERSION = -rc6
5+
EXTRAVERSION = -rc7
66
NAME = Opossums on Parade
77

88
# *DOCUMENTATION*

‎arch/arm/configs/nhk8815_defconfig

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,6 @@ CONFIG_SLAB=y
1515
CONFIG_ARCH_NOMADIK=y
1616
CONFIG_MACH_NOMADIK_8815NHK=y
1717
CONFIG_AEABI=y
18-
CONFIG_ZBOOT_ROM_TEXT=0x0
19-
CONFIG_ZBOOT_ROM_BSS=0x0
2018
CONFIG_MODULES=y
2119
CONFIG_MODULE_UNLOAD=y
2220
# CONFIG_BLK_DEV_BSG is not set
@@ -52,9 +50,9 @@ CONFIG_MTD_BLOCK=y
5250
CONFIG_MTD_ONENAND=y
5351
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
5452
CONFIG_MTD_ONENAND_GENERIC=y
55-
CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y
5653
CONFIG_MTD_RAW_NAND=y
5754
CONFIG_MTD_NAND_FSMC=y
55+
CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y
5856
CONFIG_BLK_DEV_LOOP=y
5957
CONFIG_BLK_DEV_CRYPTOLOOP=y
6058
CONFIG_BLK_DEV_RAM=y
@@ -97,6 +95,7 @@ CONFIG_REGULATOR=y
9795
CONFIG_DRM=y
9896
CONFIG_DRM_PANEL_TPO_TPG110=y
9997
CONFIG_DRM_PL111=y
98+
CONFIG_FB=y
10099
CONFIG_BACKLIGHT_CLASS_DEVICE=y
101100
CONFIG_BACKLIGHT_PWM=y
102101
CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -136,9 +135,8 @@ CONFIG_NLS_ISO8859_15=y
136135
CONFIG_CRYPTO_MD5=y
137136
CONFIG_CRYPTO_SHA1=y
138137
CONFIG_CRYPTO_DES=y
138+
# CONFIG_DEBUG_BUGVERBOSE is not set
139139
CONFIG_DEBUG_INFO=y
140-
# CONFIG_ENABLE_MUST_CHECK is not set
141140
CONFIG_DEBUG_FS=y
142141
# CONFIG_SCHED_DEBUG is not set
143142
# CONFIG_DEBUG_PREEMPT is not set
144-
# CONFIG_DEBUG_BUGVERBOSE is not set

‎arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -218,30 +218,30 @@
218218
/*
219219
* PCI Control/Status Registers
220220
*/
221-
#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
222-
223-
#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
224-
#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
225-
#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
226-
#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
227-
#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
228-
#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
229-
#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
230-
#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
231-
#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
232-
#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
233-
#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
234-
#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
235-
#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
236-
#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
237-
#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
238-
#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
239-
#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
240-
#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
241-
#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
242-
#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
243-
#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
244-
#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
221+
#define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
222+
223+
#define PCI_NP_AD _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
224+
#define PCI_NP_CBE _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
225+
#define PCI_NP_WDATA _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
226+
#define PCI_NP_RDATA _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
227+
#define PCI_CRP_AD_CBE _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
228+
#define PCI_CRP_WDATA _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
229+
#define PCI_CRP_RDATA _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
230+
#define PCI_CSR _IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
231+
#define PCI_ISR _IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
232+
#define PCI_INTEN _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
233+
#define PCI_DMACTRL _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
234+
#define PCI_AHBMEMBASE _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
235+
#define PCI_AHBIOBASE _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
236+
#define PCI_PCIMEMBASE _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
237+
#define PCI_AHBDOORBELL _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
238+
#define PCI_PCIDOORBELL _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
239+
#define PCI_ATPDMA0_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
240+
#define PCI_ATPDMA0_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
241+
#define PCI_ATPDMA0_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
242+
#define PCI_ATPDMA1_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
243+
#define PCI_ATPDMA1_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
244+
#define PCI_ATPDMA1_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
245245

246246
/*
247247
* PCI register values and bit definitions

‎arch/arm64/Makefile

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@@ -183,6 +183,8 @@ endif
183183
# We use MRPROPER_FILES and CLEAN_FILES now
184184
archclean:
185185
$(Q)$(MAKE) $(clean)=$(boot)
186+
$(Q)$(MAKE) $(clean)=arch/arm64/kernel/vdso
187+
$(Q)$(MAKE) $(clean)=arch/arm64/kernel/vdso32
186188

187189
ifeq ($(KBUILD_EXTMOD),)
188190
# We need to generate vdso-offsets.h before compiling certain files in kernel/.

‎arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts

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@@ -1,6 +1,7 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/* Copyright (c) 2015, LGE Inc. All rights reserved.
33
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
4+
* Copyright (c) 2021, Petr Vorel <[email protected]>
45
*/
56

67
/dts-v1/;
@@ -9,6 +10,9 @@
910
#include "pm8994.dtsi"
1011
#include "pmi8994.dtsi"
1112

13+
/* cont_splash_mem has different memory mapping */
14+
/delete-node/ &cont_splash_mem;
15+
1216
/ {
1317
model = "LG Nexus 5X";
1418
compatible = "lg,bullhead", "qcom,msm8992";
@@ -17,6 +21,9 @@
1721
qcom,board-id = <0xb64 0>;
1822
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
1923

24+
/* Bullhead firmware doesn't support PSCI */
25+
/delete-node/ psci;
26+
2027
aliases {
2128
serial0 = &blsp1_uart2;
2229
};
@@ -38,6 +45,11 @@
3845
ftrace-size = <0x10000>;
3946
pmsg-size = <0x20000>;
4047
};
48+
49+
cont_splash_mem: memory@3400000 {
50+
reg = <0 0x03400000 0 0x1200000>;
51+
no-map;
52+
};
4153
};
4254
};
4355

‎arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts

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@@ -1,12 +1,16 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/* Copyright (c) 2015, Huawei Inc. All rights reserved.
33
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
4+
* Copyright (c) 2021, Petr Vorel <[email protected]>
45
*/
56

67
/dts-v1/;
78

89
#include "msm8994.dtsi"
910

11+
/* Angler's firmware does not report where the memory is allocated */
12+
/delete-node/ &cont_splash_mem;
13+
1014
/ {
1115
model = "Huawei Nexus 6P";
1216
compatible = "huawei,angler", "qcom,msm8994";

‎arch/arm64/boot/dts/qcom/sc7280.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,7 @@
200200
&BIG_CPU_SLEEP_1
201201
&CLUSTER_SLEEP_0>;
202202
next-level-cache = <&L2_700>;
203-
qcom,freq-domain = <&cpufreq_hw 1>;
203+
qcom,freq-domain = <&cpufreq_hw 2>;
204204
#cooling-cells = <2>;
205205
L2_700: l2-cache {
206206
compatible = "cache";

‎arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@
6969
};
7070
rmtfs_upper_guard: memory@f5d01000 {
7171
no-map;
72-
reg = <0 0xf5d01000 0 0x2000>;
72+
reg = <0 0xf5d01000 0 0x1000>;
7373
};
7474

7575
/*
@@ -78,7 +78,7 @@
7878
*/
7979
removed_region: memory@88f00000 {
8080
no-map;
81-
reg = <0 0x88f00000 0 0x200000>;
81+
reg = <0 0x88f00000 0 0x1c00000>;
8282
};
8383

8484
ramoops: ramoops@ac300000 {

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