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sandip4nPeter Zijlstra
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perf/x86/amd/uncore: Add group exclusivity
In some cases, it may be necessary to restrict opening PMU events to a subset of CPUs. E.g. Unified Memory Controller (UMC) PMUs are specific to each active memory channel and the MSR address space for the PERF_CTL and PERF_CTR registers is reused on each socket. Thus, opening events for a specific UMC PMU should be restricted to CPUs belonging to the same socket as that of the UMC. The "cpumask" of the PMU should also reflect this accordingly. Uncore PMUs which require this can use the new group attribute in struct amd_uncore_pmu to set a valid group ID during the scan() phase. Later, during init(), an uncore context for a CPU will be unavailable if the group ID does not match. Signed-off-by: Sandipan Das <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lore.kernel.org/r/937d6d71010a48ea4e069f4904b3116a5f99ecdf.1696425185.git.sandipan.das@amd.com
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arch/x86/events/amd/uncore.c

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727

2828
#define COUNTER_SHIFT 16
2929
#define UNCORE_NAME_LEN 16
30+
#define UNCORE_GROUP_MAX 256
3031

3132
#undef pr_fmt
3233
#define pr_fmt(fmt) "amd_uncore: " fmt
@@ -45,6 +46,7 @@ struct amd_uncore_pmu {
4546
int num_counters;
4647
int rdpmc_base;
4748
u32 msr_base;
49+
int group;
4850
cpumask_t active_mask;
4951
struct pmu pmu;
5052
struct amd_uncore_ctx * __percpu *ctx;
@@ -61,6 +63,7 @@ union amd_uncore_info {
6163
struct {
6264
u64 aux_data:32; /* auxiliary data */
6365
u64 num_pmcs:8; /* number of counters */
66+
u64 gid:8; /* group id */
6467
u64 cid:8; /* context id */
6568
} split;
6669
u64 full;
@@ -371,6 +374,13 @@ int amd_uncore_ctx_cid(struct amd_uncore *uncore, unsigned int cpu)
371374
return info->split.cid;
372375
}
373376

377+
static __always_inline
378+
int amd_uncore_ctx_gid(struct amd_uncore *uncore, unsigned int cpu)
379+
{
380+
union amd_uncore_info *info = per_cpu_ptr(uncore->info, cpu);
381+
return info->split.gid;
382+
}
383+
374384
static __always_inline
375385
int amd_uncore_ctx_num_pmcs(struct amd_uncore *uncore, unsigned int cpu)
376386
{
@@ -409,18 +419,23 @@ static int amd_uncore_ctx_init(struct amd_uncore *uncore, unsigned int cpu)
409419
{
410420
struct amd_uncore_ctx *curr, *prev;
411421
struct amd_uncore_pmu *pmu;
412-
int node, cid, i, j;
422+
int node, cid, gid, i, j;
413423

414424
if (!uncore->init_done || !uncore->num_pmus)
415425
return 0;
416426

417427
cid = amd_uncore_ctx_cid(uncore, cpu);
428+
gid = amd_uncore_ctx_gid(uncore, cpu);
418429

419430
for (i = 0; i < uncore->num_pmus; i++) {
420431
pmu = &uncore->pmus[i];
421432
*per_cpu_ptr(pmu->ctx, cpu) = NULL;
422433
curr = NULL;
423434

435+
/* Check for group exclusivity */
436+
if (gid != pmu->group)
437+
continue;
438+
424439
/* Find a sibling context */
425440
for_each_online_cpu(j) {
426441
if (cpu == j)
@@ -603,6 +618,7 @@ void amd_uncore_df_ctx_scan(struct amd_uncore *uncore, unsigned int cpu)
603618

604619
info.split.aux_data = 0;
605620
info.split.num_pmcs = NUM_COUNTERS_NB;
621+
info.split.gid = 0;
606622
info.split.cid = topology_die_id(cpu);
607623

608624
if (pmu_version >= 2) {
@@ -641,6 +657,7 @@ int amd_uncore_df_ctx_init(struct amd_uncore *uncore, unsigned int cpu)
641657
pmu->num_counters = amd_uncore_ctx_num_pmcs(uncore, cpu);
642658
pmu->msr_base = MSR_F15H_NB_PERF_CTL;
643659
pmu->rdpmc_base = RDPMC_BASE_NB;
660+
pmu->group = amd_uncore_ctx_gid(uncore, cpu);
644661

645662
if (pmu_version >= 2) {
646663
*df_attr++ = &format_attr_event14v2.attr;
@@ -734,6 +751,7 @@ void amd_uncore_l3_ctx_scan(struct amd_uncore *uncore, unsigned int cpu)
734751

735752
info.split.aux_data = 0;
736753
info.split.num_pmcs = NUM_COUNTERS_L2;
754+
info.split.gid = 0;
737755
info.split.cid = get_llc_id(cpu);
738756

739757
if (boot_cpu_data.x86 >= 0x17)
@@ -770,6 +788,7 @@ int amd_uncore_l3_ctx_init(struct amd_uncore *uncore, unsigned int cpu)
770788
pmu->num_counters = amd_uncore_ctx_num_pmcs(uncore, cpu);
771789
pmu->msr_base = MSR_F16H_L2I_PERF_CTL;
772790
pmu->rdpmc_base = RDPMC_BASE_LLC;
791+
pmu->group = amd_uncore_ctx_gid(uncore, cpu);
773792

774793
if (boot_cpu_data.x86 >= 0x17) {
775794
*l3_attr++ = &format_attr_event8.attr;

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