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NishadSarafvinodkoul
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dmaengine: amd: qdma: Add AMD QDMA driver
Adds driver to enable PCIe board which uses AMD QDMA (the Queue-based Direct Memory Access) subsystem. For example, Xilinx Alveo V70 AI Accelerator devices. https://www.xilinx.com/applications/data-center/v70.html The QDMA subsystem is used in conjunction with the PCI Express IP block to provide high performance data transfer between host memory and the card's DMA subsystem. +-------+ +-------+ +-----------+ PCIe | | | | | | Tx/Rx | | | | AXI | | <=======> | PCIE | <===> | QDMA | <====>| User Logic| | | | | | | +-------+ +-------+ +-----------+ The primary mechanism to transfer data using the QDMA is for the QDMA engine to operate on instructions (descriptors) provided by the host operating system. Using the descriptors, the QDMA can move data in both the Host to Card (H2C) direction, or the Card to Host (C2H) direction. The QDMA provides a per-queue basis option whether DMA traffic goes to an AXI4 memory map (MM) interface or to an AXI4-Stream interface. The hardware detail is provided by https://docs.xilinx.com/r/en-US/pg302-qdma Implements dmaengine APIs to support MM DMA transfers. - probe the available DMA channels - use dma_slave_map for channel lookup - use virtual channel to manage dmaengine tx descriptors - implement device_prep_slave_sg callback to handle host scatter gather list Signed-off-by: Nishad Saraf <[email protected]> Signed-off-by: Lizhi Hou <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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MAINTAINERS

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S: Maintained
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F: drivers/dma/ptdma/
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AMD QDMA DRIVER
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M: Nishad Saraf <[email protected]>
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M: Lizhi Hou <[email protected]>
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S: Supported
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F: drivers/dma/amd/qdma/
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F: include/linux/platform_data/amd_qdma.h
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AMD SEATTLE DEVICE TREE SUPPORT
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M: Suravee Suthikulpanit <[email protected]>
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M: Tom Lendacky <[email protected]>

drivers/dma/Kconfig

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@@ -716,6 +716,8 @@ config XILINX_ZYNQMP_DPDMA
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display driver.
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# driver files
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source "drivers/dma/amd/Kconfig"
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source "drivers/dma/bestcomm/Kconfig"
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source "drivers/dma/mediatek/Kconfig"

drivers/dma/Makefile

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@@ -83,6 +83,7 @@ obj-$(CONFIG_ST_FDMA) += st_fdma.o
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obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
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obj-$(CONFIG_INTEL_LDMA) += lgm/
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obj-y += amd/
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obj-y += mediatek/
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obj-y += qcom/
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obj-y += stm32/

drivers/dma/amd/Kconfig

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# SPDX-License-Identifier: GPL-2.0-only
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config AMD_QDMA
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tristate "AMD Queue-based DMA"
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depends on HAS_IOMEM
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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select REGMAP_MMIO
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help
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Enable support for the AMD Queue-based DMA subsystem. The primary
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mechanism to transfer data using the QDMA is for the QDMA engine to
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operate on instructions (descriptors) provided by the host operating
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system. Using the descriptors, the QDMA can move data in either the
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Host to Card (H2C) direction or the Card to Host (C2H) direction.

drivers/dma/amd/Makefile

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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_AMD_QDMA) += qdma/

drivers/dma/amd/qdma/Makefile

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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_AMD_QDMA) += amd-qdma.o
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amd-qdma-$(CONFIG_AMD_QDMA) := qdma.o qdma-comm-regs.o

drivers/dma/amd/qdma/qdma-comm-regs.c

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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
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*/
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#ifndef __QDMA_REGS_DEF_H
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#define __QDMA_REGS_DEF_H
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#include "qdma.h"
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const struct qdma_reg qdma_regos_default[QDMA_REGO_MAX] = {
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[QDMA_REGO_CTXT_DATA] = QDMA_REGO(0x804, 8),
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[QDMA_REGO_CTXT_CMD] = QDMA_REGO(0x844, 1),
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[QDMA_REGO_CTXT_MASK] = QDMA_REGO(0x824, 8),
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[QDMA_REGO_MM_H2C_CTRL] = QDMA_REGO(0x1004, 1),
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[QDMA_REGO_MM_C2H_CTRL] = QDMA_REGO(0x1204, 1),
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[QDMA_REGO_QUEUE_COUNT] = QDMA_REGO(0x120, 1),
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[QDMA_REGO_RING_SIZE] = QDMA_REGO(0x204, 1),
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[QDMA_REGO_H2C_PIDX] = QDMA_REGO(0x18004, 1),
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[QDMA_REGO_C2H_PIDX] = QDMA_REGO(0x18008, 1),
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[QDMA_REGO_INTR_CIDX] = QDMA_REGO(0x18000, 1),
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[QDMA_REGO_FUNC_ID] = QDMA_REGO(0x12c, 1),
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[QDMA_REGO_ERR_INT] = QDMA_REGO(0xb04, 1),
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[QDMA_REGO_ERR_STAT] = QDMA_REGO(0x248, 1),
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};
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const struct qdma_reg_field qdma_regfs_default[QDMA_REGF_MAX] = {
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/* QDMA_REGO_CTXT_DATA fields */
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[QDMA_REGF_IRQ_ENABLE] = QDMA_REGF(53, 53),
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[QDMA_REGF_WBK_ENABLE] = QDMA_REGF(52, 52),
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[QDMA_REGF_WBI_CHECK] = QDMA_REGF(34, 34),
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[QDMA_REGF_IRQ_ARM] = QDMA_REGF(16, 16),
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[QDMA_REGF_IRQ_VEC] = QDMA_REGF(138, 128),
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[QDMA_REGF_IRQ_AGG] = QDMA_REGF(139, 139),
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[QDMA_REGF_WBI_INTVL_ENABLE] = QDMA_REGF(35, 35),
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[QDMA_REGF_MRKR_DISABLE] = QDMA_REGF(62, 62),
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[QDMA_REGF_QUEUE_ENABLE] = QDMA_REGF(32, 32),
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[QDMA_REGF_QUEUE_MODE] = QDMA_REGF(63, 63),
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[QDMA_REGF_DESC_BASE] = QDMA_REGF(127, 64),
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[QDMA_REGF_DESC_SIZE] = QDMA_REGF(49, 48),
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[QDMA_REGF_RING_ID] = QDMA_REGF(47, 44),
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[QDMA_REGF_QUEUE_BASE] = QDMA_REGF(11, 0),
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[QDMA_REGF_QUEUE_MAX] = QDMA_REGF(44, 32),
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[QDMA_REGF_FUNCTION_ID] = QDMA_REGF(24, 17),
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[QDMA_REGF_INTR_AGG_BASE] = QDMA_REGF(66, 15),
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[QDMA_REGF_INTR_VECTOR] = QDMA_REGF(11, 1),
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[QDMA_REGF_INTR_SIZE] = QDMA_REGF(69, 67),
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[QDMA_REGF_INTR_VALID] = QDMA_REGF(0, 0),
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[QDMA_REGF_INTR_COLOR] = QDMA_REGF(14, 14),
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[QDMA_REGF_INTR_FUNCTION_ID] = QDMA_REGF(125, 114),
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/* QDMA_REGO_CTXT_CMD fields */
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[QDMA_REGF_CMD_INDX] = QDMA_REGF(19, 7),
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[QDMA_REGF_CMD_CMD] = QDMA_REGF(6, 5),
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[QDMA_REGF_CMD_TYPE] = QDMA_REGF(4, 1),
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[QDMA_REGF_CMD_BUSY] = QDMA_REGF(0, 0),
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/* QDMA_REGO_QUEUE_COUNT fields */
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[QDMA_REGF_QUEUE_COUNT] = QDMA_REGF(11, 0),
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/* QDMA_REGO_ERR_INT fields */
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[QDMA_REGF_ERR_INT_FUNC] = QDMA_REGF(11, 0),
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[QDMA_REGF_ERR_INT_VEC] = QDMA_REGF(22, 12),
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[QDMA_REGF_ERR_INT_ARM] = QDMA_REGF(24, 24),
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};
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#endif /* __QDMA_REGS_DEF_H */

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