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net: ti: icssg-prueth: Fix buffer allocation for ICSSG
Fixes overlapping buffer allocation for ICSSG peripheral used for storing packets to be received/transmitted. There are 3 buffers: 1. Buffer for Locally Injected Packets 2. Buffer for Forwarding Packets 3. Buffer for Host Egress Packets In existing allocation buffers for 2. and 3. are overlapping causing packet corruption. Packet corruption observations: During tcp iperf testing, due to overlapping buffers the received ack packet overwrites the packet to be transmitted. So, we see packets on wire with the ack packet content inside the content of next TCP packet from sender device. Details for AM64x switch mode: -> Allocation by existing driver: +---------+-------------------------------------------------------------+ | | SLICE 0 | SLICE 1 | | +------+--------------+--------+------+--------------+--------+ | | Slot | Base Address | Size | Slot | Base Address | Size | |---------+------+--------------+--------+------+--------------+--------+ | | 0 | 70000000 | 0x2000 | 0 | 70010000 | 0x2000 | | | 1 | 70002000 | 0x2000 | 1 | 70012000 | 0x2000 | | | 2 | 70004000 | 0x2000 | 2 | 70014000 | 0x2000 | | FWD | 3 | 70006000 | 0x2000 | 3 | 70016000 | 0x2000 | | Buffers | 4 | 70008000 | 0x2000 | 4 | 70018000 | 0x2000 | | | 5 | 7000A000 | 0x2000 | 5 | 7001A000 | 0x2000 | | | 6 | 7000C000 | 0x2000 | 6 | 7001C000 | 0x2000 | | | 7 | 7000E000 | 0x2000 | 7 | 7001E000 | 0x2000 | +---------+------+--------------+--------+------+--------------+--------+ | | 8 | 70020000 | 0x1000 | 8 | 70028000 | 0x1000 | | | 9 | 70021000 | 0x1000 | 9 | 70029000 | 0x1000 | | | 10 | 70022000 | 0x1000 | 10 | 7002A000 | 0x1000 | | Our | 11 | 70023000 | 0x1000 | 11 | 7002B000 | 0x1000 | | LI | 12 | 00000000 | 0x0 | 12 | 00000000 | 0x0 | | Buffers | 13 | 00000000 | 0x0 | 13 | 00000000 | 0x0 | | | 14 | 00000000 | 0x0 | 14 | 00000000 | 0x0 | | | 15 | 00000000 | 0x0 | 15 | 00000000 | 0x0 | +---------+------+--------------+--------+------+--------------+--------+ | | 16 | 70024000 | 0x1000 | 16 | 7002C000 | 0x1000 | | | 17 | 70025000 | 0x1000 | 17 | 7002D000 | 0x1000 | | | 18 | 70026000 | 0x1000 | 18 | 7002E000 | 0x1000 | | Their | 19 | 70027000 | 0x1000 | 19 | 7002F000 | 0x1000 | | LI | 20 | 00000000 | 0x0 | 20 | 00000000 | 0x0 | | Buffers | 21 | 00000000 | 0x0 | 21 | 00000000 | 0x0 | | | 22 | 00000000 | 0x0 | 22 | 00000000 | 0x0 | | | 23 | 00000000 | 0x0 | 23 | 00000000 | 0x0 | +---------+------+--------------+--------+------+--------------+--------+ --> here 16, 17, 18, 19 overlapping with below express buffer +-----+-----------------------------------------------+ | | SLICE 0 | SLICE 1 | | +------------+----------+------------+----------+ | | Start addr | End addr | Start addr | End addr | +-----+------------+----------+------------+----------+ | EXP | 70024000 | 70028000 | 7002C000 | 70030000 | <-- Overlapping | PRE | 70030000 | 70033800 | 70034000 | 70037800 | +-----+------------+----------+------------+----------+ +---------------------+----------+----------+ | | SLICE 0 | SLICE 1 | +---------------------+----------+----------+ | Default Drop Offset | 00000000 | 00000000 | <-- Field not configured +---------------------+----------+----------+ -> Allocation this patch brings: +---------+-------------------------------------------------------------+ | | SLICE 0 | SLICE 1 | | +------+--------------+--------+------+--------------+--------+ | | Slot | Base Address | Size | Slot | Base Address | Size | |---------+------+--------------+--------+------+--------------+--------+ | | 0 | 70000000 | 0x2000 | 0 | 70040000 | 0x2000 | | | 1 | 70002000 | 0x2000 | 1 | 70042000 | 0x2000 | | | 2 | 70004000 | 0x2000 | 2 | 70044000 | 0x2000 | | FWD | 3 | 70006000 | 0x2000 | 3 | 70046000 | 0x2000 | | Buffers | 4 | 70008000 | 0x2000 | 4 | 70048000 | 0x2000 | | | 5 | 7000A000 | 0x2000 | 5 | 7004A000 | 0x2000 | | | 6 | 7000C000 | 0x2000 | 6 | 7004C000 | 0x2000 | | | 7 | 7000E000 | 0x2000 | 7 | 7004E000 | 0x2000 | +---------+------+--------------+--------+------+--------------+--------+ | | 8 | 70010000 | 0x1000 | 8 | 70050000 | 0x1000 | | | 9 | 70011000 | 0x1000 | 9 | 70051000 | 0x1000 | | | 10 | 70012000 | 0x1000 | 10 | 70052000 | 0x1000 | | Our | 11 | 70013000 | 0x1000 | 11 | 70053000 | 0x1000 | | LI | 12 | 00000000 | 0x0 | 12 | 00000000 | 0x0 | | Buffers | 13 | 00000000 | 0x0 | 13 | 00000000 | 0x0 | | | 14 | 00000000 | 0x0 | 14 | 00000000 | 0x0 | | | 15 | 00000000 | 0x0 | 15 | 00000000 | 0x0 | +---------+------+--------------+--------+------+--------------+--------+ | | 16 | 70014000 | 0x1000 | 16 | 70054000 | 0x1000 | | | 17 | 70015000 | 0x1000 | 17 | 70055000 | 0x1000 | | | 18 | 70016000 | 0x1000 | 18 | 70056000 | 0x1000 | | Their | 19 | 70017000 | 0x1000 | 19 | 70057000 | 0x1000 | | LI | 20 | 00000000 | 0x0 | 20 | 00000000 | 0x0 | | Buffers | 21 | 00000000 | 0x0 | 21 | 00000000 | 0x0 | | | 22 | 00000000 | 0x0 | 22 | 00000000 | 0x0 | | | 23 | 00000000 | 0x0 | 23 | 00000000 | 0x0 | +---------+------+--------------+--------+------+--------------+--------+ +-----+-----------------------------------------------+ | | SLICE 0 | SLICE 1 | | +------------+----------+------------+----------+ | | Start addr | End addr | Start addr | End addr | +-----+------------+----------+------------+----------+ | EXP | 70018000 | 7001C000 | 70058000 | 7005C000 | | PRE | 7001C000 | 7001F800 | 7005C000 | 7005F800 | +-----+------------+----------+------------+----------+ +---------------------+----------+----------+ | | SLICE 0 | SLICE 1 | +---------------------+----------+----------+ | Default Drop Offset | 7001F800 | 7005F800 | +---------------------+----------+----------+ Rootcause: missing buffer configuration for Express frames in function: prueth_fw_offload_buffer_setup() Details: Driver implements two distinct buffer configuration functions that are invoked based on the driver state and ICSSG firmware:- - prueth_fw_offload_buffer_setup() - prueth_emac_buffer_setup() During initialization, driver creates standard network interfaces (netdevs) and configures buffers via prueth_emac_buffer_setup(). This function properly allocates and configures all required memory regions including: - LI buffers - Express packet buffers - Preemptible packet buffers However, when the driver transitions to an offload mode (switch/HSR/PRP), buffer reconfiguration is handled by prueth_fw_offload_buffer_setup(). This function does not reconfigure the buffer regions required for Express packets, leading to incorrect buffer allocation. Fixes: abd5576 ("net: ti: icssg-prueth: Add support for ICSSG switch firmware") Signed-off-by: Himanshu Mittal <[email protected]> Reviewed-by: Simon Horman <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
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‎drivers/net/ethernet/ti/icssg/icssg_config.c‎

Lines changed: 106 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -288,52 +288,79 @@ static int prueth_fw_offload_buffer_setup(struct prueth_emac *emac)
288288
int i;
289289

290290
addr = lower_32_bits(prueth->msmcram.pa);
291-
if (slice)
292-
addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE;
291+
if (slice) {
292+
if (prueth->pdata.banked_ms_ram)
293+
addr += MSMC_RAM_BANK_SIZE;
294+
else
295+
addr += PRUETH_SW_TOTAL_BUF_SIZE_PER_SLICE;
296+
}
293297

294298
if (addr % SZ_64K) {
295299
dev_warn(prueth->dev, "buffer pool needs to be 64KB aligned\n");
296300
return -EINVAL;
297301
}
298302

299303
bpool_cfg = emac->dram.va + BUFFER_POOL_0_ADDR_OFFSET;
300-
/* workaround for f/w bug. bpool 0 needs to be initialized */
301-
for (i = 0; i < PRUETH_NUM_BUF_POOLS; i++) {
304+
305+
/* Configure buffer pools for forwarding buffers
306+
* - used by firmware to store packets to be forwarded to other port
307+
* - 8 total pools per slice
308+
*/
309+
for (i = 0; i < PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE; i++) {
302310
writel(addr, &bpool_cfg[i].addr);
303-
writel(PRUETH_EMAC_BUF_POOL_SIZE, &bpool_cfg[i].len);
304-
addr += PRUETH_EMAC_BUF_POOL_SIZE;
311+
writel(PRUETH_SW_FWD_BUF_POOL_SIZE, &bpool_cfg[i].len);
312+
addr += PRUETH_SW_FWD_BUF_POOL_SIZE;
305313
}
306314

307-
if (!slice)
308-
addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE;
309-
else
310-
addr += PRUETH_SW_NUM_BUF_POOLS_HOST * PRUETH_SW_BUF_POOL_SIZE_HOST;
311-
312-
for (i = PRUETH_NUM_BUF_POOLS;
313-
i < 2 * PRUETH_SW_NUM_BUF_POOLS_HOST + PRUETH_NUM_BUF_POOLS;
314-
i++) {
315-
/* The driver only uses first 4 queues per PRU so only initialize them */
316-
if (i % PRUETH_SW_NUM_BUF_POOLS_HOST < PRUETH_SW_NUM_BUF_POOLS_PER_PRU) {
317-
writel(addr, &bpool_cfg[i].addr);
318-
writel(PRUETH_SW_BUF_POOL_SIZE_HOST, &bpool_cfg[i].len);
319-
addr += PRUETH_SW_BUF_POOL_SIZE_HOST;
315+
/* Configure buffer pools for Local Injection buffers
316+
* - used by firmware to store packets received from host core
317+
* - 16 total pools per slice
318+
*/
319+
for (i = 0; i < PRUETH_NUM_LI_BUF_POOLS_PER_SLICE; i++) {
320+
int cfg_idx = i + PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE;
321+
322+
/* The driver only uses first 4 queues per PRU,
323+
* so only initialize buffer for them
324+
*/
325+
if ((i % PRUETH_NUM_LI_BUF_POOLS_PER_PORT_PER_SLICE)
326+
< PRUETH_SW_USED_LI_BUF_POOLS_PER_PORT_PER_SLICE) {
327+
writel(addr, &bpool_cfg[cfg_idx].addr);
328+
writel(PRUETH_SW_LI_BUF_POOL_SIZE,
329+
&bpool_cfg[cfg_idx].len);
330+
addr += PRUETH_SW_LI_BUF_POOL_SIZE;
320331
} else {
321-
writel(0, &bpool_cfg[i].addr);
322-
writel(0, &bpool_cfg[i].len);
332+
writel(0, &bpool_cfg[cfg_idx].addr);
333+
writel(0, &bpool_cfg[cfg_idx].len);
323334
}
324335
}
325336

326-
if (!slice)
327-
addr += PRUETH_SW_NUM_BUF_POOLS_HOST * PRUETH_SW_BUF_POOL_SIZE_HOST;
328-
else
329-
addr += PRUETH_EMAC_RX_CTX_BUF_SIZE;
337+
/* Express RX buffer queue
338+
* - used by firmware to store express packets to be transmitted
339+
* to the host core
340+
*/
341+
rxq_ctx = emac->dram.va + HOST_RX_Q_EXP_CONTEXT_OFFSET;
342+
for (i = 0; i < 3; i++)
343+
writel(addr, &rxq_ctx->start[i]);
344+
345+
addr += PRUETH_SW_HOST_EXP_BUF_POOL_SIZE;
346+
writel(addr, &rxq_ctx->end);
330347

348+
/* Pre-emptible RX buffer queue
349+
* - used by firmware to store preemptible packets to be transmitted
350+
* to the host core
351+
*/
331352
rxq_ctx = emac->dram.va + HOST_RX_Q_PRE_CONTEXT_OFFSET;
332353
for (i = 0; i < 3; i++)
333354
writel(addr, &rxq_ctx->start[i]);
334355

335-
addr += PRUETH_EMAC_RX_CTX_BUF_SIZE;
336-
writel(addr - SZ_2K, &rxq_ctx->end);
356+
addr += PRUETH_SW_HOST_PRE_BUF_POOL_SIZE;
357+
writel(addr, &rxq_ctx->end);
358+
359+
/* Set pointer for default dropped packet write
360+
* - used by firmware to temporarily store packet to be dropped
361+
*/
362+
rxq_ctx = emac->dram.va + DEFAULT_MSMC_Q_OFFSET;
363+
writel(addr, &rxq_ctx->start[0]);
337364

338365
return 0;
339366
}
@@ -347,53 +374,80 @@ static int prueth_emac_buffer_setup(struct prueth_emac *emac)
347374
u32 addr;
348375
int i;
349376

350-
/* Layout to have 64KB aligned buffer pool
351-
* |BPOOL0|BPOOL1|RX_CTX0|RX_CTX1|
352-
*/
353-
354377
addr = lower_32_bits(prueth->msmcram.pa);
355-
if (slice)
356-
addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE;
378+
if (slice) {
379+
if (prueth->pdata.banked_ms_ram)
380+
addr += MSMC_RAM_BANK_SIZE;
381+
else
382+
addr += PRUETH_EMAC_TOTAL_BUF_SIZE_PER_SLICE;
383+
}
357384

358385
if (addr % SZ_64K) {
359386
dev_warn(prueth->dev, "buffer pool needs to be 64KB aligned\n");
360387
return -EINVAL;
361388
}
362389

363390
bpool_cfg = emac->dram.va + BUFFER_POOL_0_ADDR_OFFSET;
364-
/* workaround for f/w bug. bpool 0 needs to be initilalized */
365-
writel(addr, &bpool_cfg[0].addr);
366-
writel(0, &bpool_cfg[0].len);
367391

368-
for (i = PRUETH_EMAC_BUF_POOL_START;
369-
i < PRUETH_EMAC_BUF_POOL_START + PRUETH_NUM_BUF_POOLS;
370-
i++) {
371-
writel(addr, &bpool_cfg[i].addr);
372-
writel(PRUETH_EMAC_BUF_POOL_SIZE, &bpool_cfg[i].len);
373-
addr += PRUETH_EMAC_BUF_POOL_SIZE;
392+
/* Configure buffer pools for forwarding buffers
393+
* - in mac mode - no forwarding so initialize all pools to 0
394+
* - 8 total pools per slice
395+
*/
396+
for (i = 0; i < PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE; i++) {
397+
writel(0, &bpool_cfg[i].addr);
398+
writel(0, &bpool_cfg[i].len);
374399
}
375400

376-
if (!slice)
377-
addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE;
378-
else
379-
addr += PRUETH_EMAC_RX_CTX_BUF_SIZE * 2;
401+
/* Configure buffer pools for Local Injection buffers
402+
* - used by firmware to store packets received from host core
403+
* - 16 total pools per slice
404+
*/
405+
bpool_cfg = emac->dram.va + BUFFER_POOL_0_ADDR_OFFSET;
406+
for (i = 0; i < PRUETH_NUM_LI_BUF_POOLS_PER_SLICE; i++) {
407+
int cfg_idx = i + PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE;
408+
409+
/* In EMAC mode, only first 4 buffers are used,
410+
* as 1 slice needs to handle only 1 port
411+
*/
412+
if (i < PRUETH_EMAC_USED_LI_BUF_POOLS_PER_PORT_PER_SLICE) {
413+
writel(addr, &bpool_cfg[cfg_idx].addr);
414+
writel(PRUETH_EMAC_LI_BUF_POOL_SIZE,
415+
&bpool_cfg[cfg_idx].len);
416+
addr += PRUETH_EMAC_LI_BUF_POOL_SIZE;
417+
} else {
418+
writel(0, &bpool_cfg[cfg_idx].addr);
419+
writel(0, &bpool_cfg[cfg_idx].len);
420+
}
421+
}
380422

381-
/* Pre-emptible RX buffer queue */
382-
rxq_ctx = emac->dram.va + HOST_RX_Q_PRE_CONTEXT_OFFSET;
423+
/* Express RX buffer queue
424+
* - used by firmware to store express packets to be transmitted
425+
* to host core
426+
*/
427+
rxq_ctx = emac->dram.va + HOST_RX_Q_EXP_CONTEXT_OFFSET;
383428
for (i = 0; i < 3; i++)
384429
writel(addr, &rxq_ctx->start[i]);
385430

386-
addr += PRUETH_EMAC_RX_CTX_BUF_SIZE;
431+
addr += PRUETH_EMAC_HOST_EXP_BUF_POOL_SIZE;
387432
writel(addr, &rxq_ctx->end);
388433

389-
/* Express RX buffer queue */
390-
rxq_ctx = emac->dram.va + HOST_RX_Q_EXP_CONTEXT_OFFSET;
434+
/* Pre-emptible RX buffer queue
435+
* - used by firmware to store preemptible packets to be transmitted
436+
* to host core
437+
*/
438+
rxq_ctx = emac->dram.va + HOST_RX_Q_PRE_CONTEXT_OFFSET;
391439
for (i = 0; i < 3; i++)
392440
writel(addr, &rxq_ctx->start[i]);
393441

394-
addr += PRUETH_EMAC_RX_CTX_BUF_SIZE;
442+
addr += PRUETH_EMAC_HOST_PRE_BUF_POOL_SIZE;
395443
writel(addr, &rxq_ctx->end);
396444

445+
/* Set pointer for default dropped packet write
446+
* - used by firmware to temporarily store packet to be dropped
447+
*/
448+
rxq_ctx = emac->dram.va + DEFAULT_MSMC_Q_OFFSET;
449+
writel(addr, &rxq_ctx->start[0]);
450+
397451
return 0;
398452
}
399453

‎drivers/net/ethernet/ti/icssg/icssg_config.h‎

Lines changed: 65 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -26,21 +26,71 @@ struct icssg_flow_cfg {
2626
#define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */
2727
#define PRUETH_RX_FLOW_DATA 0
2828

29-
#define PRUETH_EMAC_BUF_POOL_SIZE SZ_8K
30-
#define PRUETH_EMAC_POOLS_PER_SLICE 24
31-
#define PRUETH_EMAC_BUF_POOL_START 8
32-
#define PRUETH_NUM_BUF_POOLS 8
33-
#define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */
34-
#define MSMC_RAM_SIZE \
35-
(2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \
36-
PRUETH_EMAC_RX_CTX_BUF_SIZE * 2))
37-
38-
#define PRUETH_SW_BUF_POOL_SIZE_HOST SZ_4K
39-
#define PRUETH_SW_NUM_BUF_POOLS_HOST 8
40-
#define PRUETH_SW_NUM_BUF_POOLS_PER_PRU 4
41-
#define MSMC_RAM_SIZE_SWITCH_MODE \
42-
(MSMC_RAM_SIZE + \
43-
(2 * PRUETH_SW_BUF_POOL_SIZE_HOST * PRUETH_SW_NUM_BUF_POOLS_HOST))
29+
/* Defines for forwarding path buffer pools:
30+
* - used by firmware to store packets to be forwarded to other port
31+
* - 8 total pools per slice
32+
* - only used in switch mode (as no forwarding in mac mode)
33+
*/
34+
#define PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE 8
35+
#define PRUETH_SW_FWD_BUF_POOL_SIZE (SZ_8K)
36+
37+
/* Defines for local injection path buffer pools:
38+
* - used by firmware to store packets received from host core
39+
* - 16 total pools per slice
40+
* - 8 pools per port per slice and each slice handles both ports
41+
* - only 4 out of 8 pools used per port (as only 4 real QoS levels in ICSSG)
42+
* - switch mode: 8 total pools used
43+
* - mac mode: 4 total pools used
44+
*/
45+
#define PRUETH_NUM_LI_BUF_POOLS_PER_SLICE 16
46+
#define PRUETH_NUM_LI_BUF_POOLS_PER_PORT_PER_SLICE 8
47+
#define PRUETH_SW_LI_BUF_POOL_SIZE SZ_4K
48+
#define PRUETH_SW_USED_LI_BUF_POOLS_PER_SLICE 8
49+
#define PRUETH_SW_USED_LI_BUF_POOLS_PER_PORT_PER_SLICE 4
50+
#define PRUETH_EMAC_LI_BUF_POOL_SIZE SZ_8K
51+
#define PRUETH_EMAC_USED_LI_BUF_POOLS_PER_SLICE 4
52+
#define PRUETH_EMAC_USED_LI_BUF_POOLS_PER_PORT_PER_SLICE 4
53+
54+
/* Defines for host egress path - express and preemptible buffers
55+
* - used by firmware to store express and preemptible packets
56+
* to be transmitted to host core
57+
* - used by both mac/switch modes
58+
*/
59+
#define PRUETH_SW_HOST_EXP_BUF_POOL_SIZE SZ_16K
60+
#define PRUETH_SW_HOST_PRE_BUF_POOL_SIZE (SZ_16K - SZ_2K)
61+
#define PRUETH_EMAC_HOST_EXP_BUF_POOL_SIZE PRUETH_SW_HOST_EXP_BUF_POOL_SIZE
62+
#define PRUETH_EMAC_HOST_PRE_BUF_POOL_SIZE PRUETH_SW_HOST_PRE_BUF_POOL_SIZE
63+
64+
/* Buffer used by firmware to temporarily store packet to be dropped */
65+
#define PRUETH_SW_DROP_PKT_BUF_SIZE SZ_2K
66+
#define PRUETH_EMAC_DROP_PKT_BUF_SIZE PRUETH_SW_DROP_PKT_BUF_SIZE
67+
68+
/* Total switch mode memory usage for buffers per slice */
69+
#define PRUETH_SW_TOTAL_BUF_SIZE_PER_SLICE \
70+
(PRUETH_SW_FWD_BUF_POOL_SIZE * PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE + \
71+
PRUETH_SW_LI_BUF_POOL_SIZE * PRUETH_SW_USED_LI_BUF_POOLS_PER_SLICE + \
72+
PRUETH_SW_HOST_EXP_BUF_POOL_SIZE + \
73+
PRUETH_SW_HOST_PRE_BUF_POOL_SIZE + \
74+
PRUETH_SW_DROP_PKT_BUF_SIZE)
75+
76+
/* Total switch mode memory usage for all buffers */
77+
#define PRUETH_SW_TOTAL_BUF_SIZE \
78+
(2 * PRUETH_SW_TOTAL_BUF_SIZE_PER_SLICE)
79+
80+
/* Total mac mode memory usage for buffers per slice */
81+
#define PRUETH_EMAC_TOTAL_BUF_SIZE_PER_SLICE \
82+
(PRUETH_EMAC_LI_BUF_POOL_SIZE * \
83+
PRUETH_EMAC_USED_LI_BUF_POOLS_PER_SLICE + \
84+
PRUETH_EMAC_HOST_EXP_BUF_POOL_SIZE + \
85+
PRUETH_EMAC_HOST_PRE_BUF_POOL_SIZE + \
86+
PRUETH_EMAC_DROP_PKT_BUF_SIZE)
87+
88+
/* Total mac mode memory usage for all buffers */
89+
#define PRUETH_EMAC_TOTAL_BUF_SIZE \
90+
(2 * PRUETH_EMAC_TOTAL_BUF_SIZE_PER_SLICE)
91+
92+
/* Size of 1 bank of MSMC/OC_SRAM memory */
93+
#define MSMC_RAM_BANK_SIZE SZ_256K
4494

4595
#define PRUETH_SWITCH_FDB_MASK ((SIZE_OF_FDB / NUMBER_OF_FDB_BUCKET_ENTRIES) - 1)
4696

‎drivers/net/ethernet/ti/icssg/icssg_prueth.c‎

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1764,10 +1764,15 @@ static int prueth_probe(struct platform_device *pdev)
17641764
goto put_mem;
17651765
}
17661766

1767-
msmc_ram_size = MSMC_RAM_SIZE;
17681767
prueth->is_switchmode_supported = prueth->pdata.switch_mode;
1769-
if (prueth->is_switchmode_supported)
1770-
msmc_ram_size = MSMC_RAM_SIZE_SWITCH_MODE;
1768+
if (prueth->pdata.banked_ms_ram) {
1769+
/* Reserve 2 MSMC RAM banks for buffers to avoid arbitration */
1770+
msmc_ram_size = (2 * MSMC_RAM_BANK_SIZE);
1771+
} else {
1772+
msmc_ram_size = PRUETH_EMAC_TOTAL_BUF_SIZE;
1773+
if (prueth->is_switchmode_supported)
1774+
msmc_ram_size = PRUETH_SW_TOTAL_BUF_SIZE;
1775+
}
17711776

17721777
/* NOTE: FW bug needs buffer base to be 64KB aligned */
17731778
prueth->msmcram.va =
@@ -1924,7 +1929,8 @@ static int prueth_probe(struct platform_device *pdev)
19241929

19251930
free_pool:
19261931
gen_pool_free(prueth->sram_pool,
1927-
(unsigned long)prueth->msmcram.va, msmc_ram_size);
1932+
(unsigned long)prueth->msmcram.va,
1933+
prueth->msmcram.size);
19281934

19291935
put_mem:
19301936
pruss_release_mem_region(prueth->pruss, &prueth->shram);
@@ -1976,8 +1982,8 @@ static void prueth_remove(struct platform_device *pdev)
19761982
icss_iep_put(prueth->iep0);
19771983

19781984
gen_pool_free(prueth->sram_pool,
1979-
(unsigned long)prueth->msmcram.va,
1980-
MSMC_RAM_SIZE);
1985+
(unsigned long)prueth->msmcram.va,
1986+
prueth->msmcram.size);
19811987

19821988
pruss_release_mem_region(prueth->pruss, &prueth->shram);
19831989

@@ -1994,12 +2000,14 @@ static const struct prueth_pdata am654_icssg_pdata = {
19942000
.fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
19952001
.quirk_10m_link_issue = 1,
19962002
.switch_mode = 1,
2003+
.banked_ms_ram = 0,
19972004
};
19982005

19992006
static const struct prueth_pdata am64x_icssg_pdata = {
20002007
.fdqring_mode = K3_RINGACC_RING_MODE_RING,
20012008
.quirk_10m_link_issue = 1,
20022009
.switch_mode = 1,
2010+
.banked_ms_ram = 1,
20032011
};
20042012

20052013
static const struct of_device_id prueth_dt_match[] = {

‎drivers/net/ethernet/ti/icssg/icssg_prueth.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -251,11 +251,13 @@ struct prueth_emac {
251251
* @fdqring_mode: Free desc queue mode
252252
* @quirk_10m_link_issue: 10M link detect errata
253253
* @switch_mode: switch firmware support
254+
* @banked_ms_ram: banked memory support
254255
*/
255256
struct prueth_pdata {
256257
enum k3_ring_mode fdqring_mode;
257258
u32 quirk_10m_link_issue:1;
258259
u32 switch_mode:1;
260+
u32 banked_ms_ram:1;
259261
};
260262

261263
struct icssg_firmwares {

‎drivers/net/ethernet/ti/icssg/icssg_switch_map.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -180,6 +180,9 @@
180180
/* Used to notify the FW of the current link speed */
181181
#define PORT_LINK_SPEED_OFFSET 0x00A8
182182

183+
/* 2k memory pointer reserved for default writes by PRU0*/
184+
#define DEFAULT_MSMC_Q_OFFSET 0x00AC
185+
183186
/* TAS gate mask for windows list0 */
184187
#define TAS_GATE_MASK_LIST0 0x0100
185188

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