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mranostayvinodkoul
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dmaengine: ti: k3-psil: add additional TX threads for j721e
Add matching PSI-L threads mapping for transmission DMA channels on the J721E platform. Signed-off-by: Matt Ranostay <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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drivers/dma/ti/k3-psil-j721e.c

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@@ -266,6 +266,69 @@ static struct psil_ep j721e_dst_ep_map[] = {
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PSIL_ETHERNET(0xc205),
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PSIL_ETHERNET(0xc206),
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PSIL_ETHERNET(0xc207),
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/* PDMA6 (PSIL_PDMA_MCASP_G0) - McASP0-2 */
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PSIL_PDMA_MCASP(0xc400),
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PSIL_PDMA_MCASP(0xc401),
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PSIL_PDMA_MCASP(0xc402),
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/* PDMA7 (PSIL_PDMA_MCASP_G1) - McASP3-11 */
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PSIL_PDMA_MCASP(0xc500),
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PSIL_PDMA_MCASP(0xc501),
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PSIL_PDMA_MCASP(0xc502),
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PSIL_PDMA_MCASP(0xc503),
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PSIL_PDMA_MCASP(0xc504),
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PSIL_PDMA_MCASP(0xc505),
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PSIL_PDMA_MCASP(0xc506),
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PSIL_PDMA_MCASP(0xc507),
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PSIL_PDMA_MCASP(0xc508),
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/* PDMA8 (PDMA_MISC_G0) - SPI0-1 */
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PSIL_PDMA_XY_PKT(0xc600),
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PSIL_PDMA_XY_PKT(0xc601),
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PSIL_PDMA_XY_PKT(0xc602),
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PSIL_PDMA_XY_PKT(0xc603),
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PSIL_PDMA_XY_PKT(0xc604),
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PSIL_PDMA_XY_PKT(0xc605),
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PSIL_PDMA_XY_PKT(0xc606),
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PSIL_PDMA_XY_PKT(0xc607),
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/* PDMA9 (PDMA_MISC_G1) - SPI2-3 */
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PSIL_PDMA_XY_PKT(0xc60c),
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PSIL_PDMA_XY_PKT(0xc60d),
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PSIL_PDMA_XY_PKT(0xc60e),
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PSIL_PDMA_XY_PKT(0xc60f),
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PSIL_PDMA_XY_PKT(0xc610),
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PSIL_PDMA_XY_PKT(0xc611),
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PSIL_PDMA_XY_PKT(0xc612),
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PSIL_PDMA_XY_PKT(0xc613),
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/* PDMA10 (PDMA_MISC_G2) - SPI4-5 */
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PSIL_PDMA_XY_PKT(0xc618),
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PSIL_PDMA_XY_PKT(0xc619),
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PSIL_PDMA_XY_PKT(0xc61a),
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PSIL_PDMA_XY_PKT(0xc61b),
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PSIL_PDMA_XY_PKT(0xc61c),
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PSIL_PDMA_XY_PKT(0xc61d),
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PSIL_PDMA_XY_PKT(0xc61e),
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PSIL_PDMA_XY_PKT(0xc61f),
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/* PDMA11 (PDMA_MISC_G3) */
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PSIL_PDMA_XY_PKT(0xc624),
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PSIL_PDMA_XY_PKT(0xc625),
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PSIL_PDMA_XY_PKT(0xc626),
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PSIL_PDMA_XY_PKT(0xc627),
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PSIL_PDMA_XY_PKT(0xc628),
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PSIL_PDMA_XY_PKT(0xc629),
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PSIL_PDMA_XY_PKT(0xc630),
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PSIL_PDMA_XY_PKT(0xc63a),
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/* PDMA13 (PDMA_USART_G0) - UART0-1 */
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PSIL_PDMA_XY_PKT(0xc700),
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PSIL_PDMA_XY_PKT(0xc701),
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/* PDMA14 (PDMA_USART_G1) - UART2-3 */
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PSIL_PDMA_XY_PKT(0xc702),
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PSIL_PDMA_XY_PKT(0xc703),
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/* PDMA15 (PDMA_USART_G2) - UART4-9 */
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PSIL_PDMA_XY_PKT(0xc704),
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PSIL_PDMA_XY_PKT(0xc705),
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PSIL_PDMA_XY_PKT(0xc706),
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PSIL_PDMA_XY_PKT(0xc707),
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PSIL_PDMA_XY_PKT(0xc708),
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PSIL_PDMA_XY_PKT(0xc709),
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/* CPSW9 */
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PSIL_ETHERNET(0xca00),
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PSIL_ETHERNET(0xca01),
@@ -284,6 +347,22 @@ static struct psil_ep j721e_dst_ep_map[] = {
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PSIL_ETHERNET(0xf005),
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PSIL_ETHERNET(0xf006),
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PSIL_ETHERNET(0xf007),
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/* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
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PSIL_PDMA_XY_PKT(0xf100),
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PSIL_PDMA_XY_PKT(0xf101),
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PSIL_PDMA_XY_PKT(0xf102),
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PSIL_PDMA_XY_PKT(0xf103),
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/* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
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PSIL_PDMA_XY_PKT(0xf200),
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PSIL_PDMA_XY_PKT(0xf201),
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PSIL_PDMA_XY_PKT(0xf202),
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PSIL_PDMA_XY_PKT(0xf203),
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PSIL_PDMA_XY_PKT(0xf204),
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PSIL_PDMA_XY_PKT(0xf205),
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PSIL_PDMA_XY_PKT(0xf206),
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PSIL_PDMA_XY_PKT(0xf207),
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/* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
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PSIL_PDMA_XY_PKT(0xf300),
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/* SA2UL */
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PSIL_SA2UL(0xf500, 1),
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PSIL_SA2UL(0xf501, 1),

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