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Paolo Abeni
committed
Merge branch 'support-one-ptp-device-per-hardware-clock'
Tariq Toukan says: ==================== Support one PTP device per hardware clock This series contains two features from Jianbo, followed by simple cleanups. Patches 1-9 by Jianbo add support for one PTP device per hardware clock, described below [1]. Patches 10-12 by Jianbo add support for 200Gbps per-lane link modes in kernel and mlx5 driver. Patches 13-15 are simple cleanups by Gal and Carolina. [1] PHC (PTP hardware clock) is normally shared by multiple functions (PF/VF/SF). mlx5 driver currently creates a separate PTP device for each network interface that shares one PHC. PHC can be configured to work as free running mode or real time mode. In this series, only one PTP device is created for the shared PHC when it is running in real time mode. To support this feature, * Firmware needs to support clock identity. When functions share a PHC, the clock identities they query are same. * Driver dynamically allocates mlx5_clock to represent a PHC. * New devcom component is added for hardware clock. Functions are grouped by the identity, and one mlx5_clock is allocated and shared by the functions with the same identity. * When PTP device accesses PHC by its callbacks, the first function in the clock devcom list is selected to send commands to firmware. * PPS IN event is armed on one function. It should be re-armed on the other one when current is unloaded. ==================== Link: https://patch.msgid.link/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2 parents 3924fa9 + 689805d commit 5f9e5d2

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20 files changed

+701
-172
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20 files changed

+701
-172
lines changed

‎drivers/net/ethernet/mellanox/mlx5/core/en/port.c

Lines changed: 54 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -296,11 +296,16 @@ enum mlx5e_fec_supported_link_mode {
296296
MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X,
297297
MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X,
298298
MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X,
299+
MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X,
300+
MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X,
301+
MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X,
302+
MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X,
299303
MLX5E_MAX_FEC_SUPPORTED_LINK_MODE,
300304
};
301305

302306
#define MLX5E_FEC_FIRST_50G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X
303307
#define MLX5E_FEC_FIRST_100G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X
308+
#define MLX5E_FEC_FIRST_200G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X
304309

305310
#define MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, policy, write, link) \
306311
do { \
@@ -320,8 +325,10 @@ static bool mlx5e_is_fec_supported_link_mode(struct mlx5_core_dev *dev,
320325
return link_mode < MLX5E_FEC_FIRST_50G_PER_LANE_MODE ||
321326
(link_mode < MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&
322327
MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm)) ||
323-
(link_mode >= MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&
324-
MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm));
328+
(link_mode < MLX5E_FEC_FIRST_200G_PER_LANE_MODE &&
329+
MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm)) ||
330+
(link_mode >= MLX5E_FEC_FIRST_200G_PER_LANE_MODE &&
331+
MLX5_CAP_PCAM_FEATURE(dev, fec_200G_per_lane_in_pplm));
325332
}
326333

327334
/* get/set FEC admin field for a given speed */
@@ -368,6 +375,18 @@ static int mlx5e_fec_admin_field(u32 *pplm, u16 *fec_policy, bool write,
368375
case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:
369376
MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_8x);
370377
break;
378+
case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X:
379+
MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 200g_1x);
380+
break;
381+
case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X:
382+
MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 400g_2x);
383+
break;
384+
case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X:
385+
MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_4x);
386+
break;
387+
case MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X:
388+
MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 1600g_8x);
389+
break;
371390
default:
372391
return -EINVAL;
373392
}
@@ -421,6 +440,18 @@ static int mlx5e_get_fec_cap_field(u32 *pplm, u16 *fec_cap,
421440
case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:
422441
*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_8x);
423442
break;
443+
case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X:
444+
*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 200g_1x);
445+
break;
446+
case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X:
447+
*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 400g_2x);
448+
break;
449+
case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X:
450+
*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_4x);
451+
break;
452+
case MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X:
453+
*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 1600g_8x);
454+
break;
424455
default:
425456
return -EINVAL;
426457
}
@@ -494,6 +525,26 @@ int mlx5e_get_fec_mode(struct mlx5_core_dev *dev, u32 *fec_mode_active,
494525
return 0;
495526
}
496527

528+
static u16 mlx5e_remap_fec_conf_mode(enum mlx5e_fec_supported_link_mode link_mode,
529+
u16 conf_fec)
530+
{
531+
/* RS fec in ethtool is originally mapped to MLX5E_FEC_RS_528_514.
532+
* For link modes up to 25G per lane, the value is kept.
533+
* For 50G or 100G per lane, it's remapped to MLX5E_FEC_RS_544_514.
534+
* For 200G per lane, remapped to MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD.
535+
*/
536+
if (conf_fec != BIT(MLX5E_FEC_RS_528_514))
537+
return conf_fec;
538+
539+
if (link_mode >= MLX5E_FEC_FIRST_200G_PER_LANE_MODE)
540+
return BIT(MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD);
541+
542+
if (link_mode >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE)
543+
return BIT(MLX5E_FEC_RS_544_514);
544+
545+
return conf_fec;
546+
}
547+
497548
int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy)
498549
{
499550
bool fec_50g_per_lane = MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm);
@@ -530,14 +581,7 @@ int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy)
530581
if (!mlx5e_is_fec_supported_link_mode(dev, i))
531582
break;
532583

533-
/* RS fec in ethtool is mapped to MLX5E_FEC_RS_528_514
534-
* to link modes up to 25G per lane and to
535-
* MLX5E_FEC_RS_544_514 in the new link modes based on
536-
* 50G or 100G per lane
537-
*/
538-
if (conf_fec == (1 << MLX5E_FEC_RS_528_514) &&
539-
i >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE)
540-
conf_fec = (1 << MLX5E_FEC_RS_544_514);
584+
conf_fec = mlx5e_remap_fec_conf_mode(i, conf_fec);
541585

542586
mlx5e_get_fec_cap_field(out, &fec_caps, i);
543587

‎drivers/net/ethernet/mellanox/mlx5/core/en/port.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@ enum {
6161
MLX5E_FEC_NOFEC,
6262
MLX5E_FEC_FIRECODE,
6363
MLX5E_FEC_RS_528_514,
64+
MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD = 4,
6465
MLX5E_FEC_RS_544_514 = 7,
6566
MLX5E_FEC_LLRS_272_257_1 = 9,
6667
};

‎drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@ static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, int txq_ix,
326326
int node;
327327

328328
sq->pdev = c->pdev;
329-
sq->clock = &mdev->clock;
329+
sq->clock = mdev->clock;
330330
sq->mkey_be = c->mkey_be;
331331
sq->netdev = c->netdev;
332332
sq->priv = c->priv;
@@ -696,7 +696,7 @@ static int mlx5e_init_ptp_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
696696
rq->pdev = c->pdev;
697697
rq->netdev = priv->netdev;
698698
rq->priv = priv;
699-
rq->clock = &mdev->clock;
699+
rq->clock = mdev->clock;
700700
rq->tstamp = &priv->tstamp;
701701
rq->mdev = mdev;
702702
rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);

‎drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -73,11 +73,6 @@ struct mlx5e_tc_act {
7373
bool is_terminating_action;
7474
};
7575

76-
struct mlx5e_tc_flow_action {
77-
unsigned int num_entries;
78-
struct flow_action_entry **entries;
79-
};
80-
8176
extern struct mlx5e_tc_act mlx5e_tc_act_drop;
8277
extern struct mlx5e_tc_act mlx5e_tc_act_trap;
8378
extern struct mlx5e_tc_act mlx5e_tc_act_accept;

‎drivers/net/ethernet/mellanox/mlx5/core/en/trap.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ static void mlx5e_init_trap_rq(struct mlx5e_trap *t, struct mlx5e_params *params
4646
rq->pdev = t->pdev;
4747
rq->netdev = priv->netdev;
4848
rq->priv = priv;
49-
rq->clock = &mdev->clock;
49+
rq->clock = mdev->clock;
5050
rq->tstamp = &priv->tstamp;
5151
rq->mdev = mdev;
5252
rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);

‎drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -289,9 +289,9 @@ static u64 mlx5e_xsk_fill_timestamp(void *_priv)
289289
ts = get_cqe_ts(priv->cqe);
290290

291291
if (mlx5_is_real_time_rq(priv->cq->mdev) || mlx5_is_real_time_sq(priv->cq->mdev))
292-
return mlx5_real_time_cyc2time(&priv->cq->mdev->clock, ts);
292+
return mlx5_real_time_cyc2time(priv->cq->mdev->clock, ts);
293293

294-
return mlx5_timecounter_cyc2time(&priv->cq->mdev->clock, ts);
294+
return mlx5_timecounter_cyc2time(priv->cq->mdev->clock, ts);
295295
}
296296

297297
static void mlx5e_xsk_request_checksum(u16 csum_start, u16 csum_offset, void *priv)

‎drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ static int mlx5e_init_xsk_rq(struct mlx5e_channel *c,
7272
rq->netdev = c->netdev;
7373
rq->priv = c->priv;
7474
rq->tstamp = c->tstamp;
75-
rq->clock = &mdev->clock;
75+
rq->clock = mdev->clock;
7676
rq->icosq = &c->icosq;
7777
rq->ix = c->ix;
7878
rq->channel = c;

‎drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -237,6 +237,27 @@ void mlx5e_build_ptys2ethtool_map(void)
237237
ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT,
238238
ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT,
239239
ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT);
240+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_1_200GBASE_CR1_KR1, ext,
241+
ETHTOOL_LINK_MODE_200000baseCR_Full_BIT,
242+
ETHTOOL_LINK_MODE_200000baseKR_Full_BIT,
243+
ETHTOOL_LINK_MODE_200000baseDR_Full_BIT,
244+
ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT,
245+
ETHTOOL_LINK_MODE_200000baseSR_Full_BIT,
246+
ETHTOOL_LINK_MODE_200000baseVR_Full_BIT);
247+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_2_400GBASE_CR2_KR2, ext,
248+
ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT,
249+
ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT,
250+
ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT,
251+
ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT,
252+
ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT,
253+
ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT);
254+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_4_800GBASE_CR4_KR4, ext,
255+
ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT,
256+
ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT,
257+
ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT,
258+
ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT,
259+
ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT,
260+
ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT);
240261
}
241262

242263
static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
@@ -931,6 +952,7 @@ static const u32 pplm_fec_2_ethtool[] = {
931952
[MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
932953
[MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
933954
[MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
955+
[MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD] = ETHTOOL_FEC_RS,
934956
};
935957

936958
static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)

‎drivers/net/ethernet/mellanox/mlx5/core/en_main.c

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -737,7 +737,7 @@ static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *param
737737
rq->netdev = c->netdev;
738738
rq->priv = c->priv;
739739
rq->tstamp = c->tstamp;
740-
rq->clock = &mdev->clock;
740+
rq->clock = mdev->clock;
741741
rq->icosq = &c->icosq;
742742
rq->ix = c->ix;
743743
rq->channel = c;
@@ -1614,7 +1614,7 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
16141614
int err;
16151615

16161616
sq->pdev = c->pdev;
1617-
sq->clock = &mdev->clock;
1617+
sq->clock = mdev->clock;
16181618
sq->mkey_be = c->mkey_be;
16191619
sq->netdev = c->netdev;
16201620
sq->mdev = c->mdev;
@@ -3816,8 +3816,11 @@ static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
38163816
/* MQPRIO is another toplevel qdisc that can't be attached
38173817
* simultaneously with the offloaded HTB.
38183818
*/
3819-
if (WARN_ON(mlx5e_selq_is_htb_enabled(&priv->selq)))
3820-
return -EINVAL;
3819+
if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
3820+
NL_SET_ERR_MSG_MOD(mqprio->extack,
3821+
"MQPRIO cannot be configured when HTB offload is enabled.");
3822+
return -EOPNOTSUPP;
3823+
}
38213824

38223825
switch (mqprio->mode) {
38233826
case TC_MQPRIO_MODE_DCB:

‎drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ static int mlx5_lag_create_port_sel_table(struct mlx5_lag *ldev,
9797
mlx5_del_flow_rules(lag_definer->rules[idx]);
9898
}
9999
j = ldev->buckets;
100-
};
100+
}
101101
goto destroy_fg;
102102
}
103103
}

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