|
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/phy/marvell,comphy-cp110.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Marvell MVEBU COMPHY Controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Miquel Raynal <[email protected]> |
| 11 | + |
| 12 | +description: > |
| 13 | + COMPHY controllers can be found on the following Marvell MVEBU SoCs: |
| 14 | +
|
| 15 | + * Armada 7k/8k (on the CP110) |
| 16 | + * Armada 3700 |
| 17 | +
|
| 18 | + It provides a number of shared PHYs used by various interfaces (network, SATA, |
| 19 | + USB, PCIe...). |
| 20 | +
|
| 21 | +properties: |
| 22 | + compatible: |
| 23 | + enum: |
| 24 | + - marvell,comphy-cp110 |
| 25 | + - marvell,comphy-a3700 |
| 26 | + |
| 27 | + reg: |
| 28 | + minItems: 1 |
| 29 | + items: |
| 30 | + - description: Generic COMPHY registers |
| 31 | + - description: Lane 1 (PCIe/GbE) registers (Armada 3700) |
| 32 | + - description: Lane 0 (USB3/GbE) registers (Armada 3700) |
| 33 | + - description: Lane 2 (SATA/USB3) registers (Armada 3700) |
| 34 | + |
| 35 | + reg-names: |
| 36 | + minItems: 1 |
| 37 | + items: |
| 38 | + - const: comphy |
| 39 | + - const: lane1_pcie_gbe |
| 40 | + - const: lane0_usb3_gbe |
| 41 | + - const: lane2_sata_usb3 |
| 42 | + |
| 43 | + '#address-cells': |
| 44 | + const: 1 |
| 45 | + |
| 46 | + '#size-cells': |
| 47 | + const: 0 |
| 48 | + |
| 49 | + clocks: |
| 50 | + maxItems: 3 |
| 51 | + description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock |
| 52 | + |
| 53 | + clock-names: |
| 54 | + items: |
| 55 | + - const: mg_clk |
| 56 | + - const: mg_core_clk |
| 57 | + - const: axi_clk |
| 58 | + |
| 59 | + marvell,system-controller: |
| 60 | + description: Phandle to the Marvell system controller (CP110 only) |
| 61 | + $ref: /schemas/types.yaml#/definitions/phandle |
| 62 | + |
| 63 | +patternProperties: |
| 64 | + '^phy@[0-2]$': |
| 65 | + description: A COMPHY lane child node |
| 66 | + type: object |
| 67 | + additionalProperties: false |
| 68 | + |
| 69 | + properties: |
| 70 | + reg: |
| 71 | + description: COMPHY lane number |
| 72 | + |
| 73 | + '#phy-cells': |
| 74 | + const: 1 |
| 75 | + |
| 76 | + required: |
| 77 | + - reg |
| 78 | + - '#phy-cells' |
| 79 | + |
| 80 | +required: |
| 81 | + - compatible |
| 82 | + - reg |
| 83 | + |
| 84 | +additionalProperties: false |
| 85 | + |
| 86 | +allOf: |
| 87 | + - if: |
| 88 | + properties: |
| 89 | + compatible: |
| 90 | + const: marvell,comphy-a3700 |
| 91 | + |
| 92 | + then: |
| 93 | + properties: |
| 94 | + clocks: false |
| 95 | + clock-names: false |
| 96 | + |
| 97 | + required: |
| 98 | + - reg-names |
| 99 | + |
| 100 | + else: |
| 101 | + required: |
| 102 | + - marvell,system-controller |
| 103 | + |
| 104 | +examples: |
| 105 | + - | |
| 106 | + phy@120000 { |
| 107 | + compatible = "marvell,comphy-cp110"; |
| 108 | + reg = <0x120000 0x6000>; |
| 109 | + clocks = <&clk 1 5>, <&clk 1 6>, <&clk 1 18>; |
| 110 | + clock-names = "mg_clk", "mg_core_clk", "axi_clk"; |
| 111 | + #address-cells = <1>; |
| 112 | + #size-cells = <0>; |
| 113 | + marvell,system-controller = <&syscon0>; |
| 114 | +
|
| 115 | + phy@0 { |
| 116 | + reg = <0>; |
| 117 | + #phy-cells = <1>; |
| 118 | + }; |
| 119 | +
|
| 120 | + phy@1 { |
| 121 | + reg = <1>; |
| 122 | + #phy-cells = <1>; |
| 123 | + }; |
| 124 | + }; |
| 125 | +
|
| 126 | + - | |
| 127 | + phy@18300 { |
| 128 | + compatible = "marvell,comphy-a3700"; |
| 129 | + reg = <0x18300 0x300>, |
| 130 | + <0x1F000 0x400>, |
| 131 | + <0x5C000 0x400>, |
| 132 | + <0xe0178 0x8>; |
| 133 | + reg-names = "comphy", |
| 134 | + "lane1_pcie_gbe", |
| 135 | + "lane0_usb3_gbe", |
| 136 | + "lane2_sata_usb3"; |
| 137 | + #address-cells = <1>; |
| 138 | + #size-cells = <0>; |
| 139 | +
|
| 140 | + comphy0: phy@0 { |
| 141 | + reg = <0>; |
| 142 | + #phy-cells = <1>; |
| 143 | + }; |
| 144 | +
|
| 145 | + comphy1: phy@1 { |
| 146 | + reg = <1>; |
| 147 | + #phy-cells = <1>; |
| 148 | + }; |
| 149 | +
|
| 150 | + comphy2: phy@2 { |
| 151 | + reg = <2>; |
| 152 | + #phy-cells = <1>; |
| 153 | + }; |
| 154 | + }; |
0 commit comments