drm/i915: Reoder gen9+ timestamp freq register bits

We customarily define the bits of a register in big endian
order. Reorder the gen9+ timestamp freq register bits to match.

Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

Author: vsyrjala

drivers/gpu/drm/i915/gt/intel_gt_regs.h

@@ -30,14 +30,14 @@
 
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0				_MMIO(0xd00)
-#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	REG_BIT(3)
-#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
 #define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	REG_GENMASK(5, 3)
 #define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
 #define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
 #define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)
 #define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ	REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)
+#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	REG_BIT(3)
+#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
+#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
 #define   GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	REG_GENMASK(2, 1)
 
 #define RPM_CONFIG1				_MMIO(0xd04)
@@ -879,10 +879,10 @@
 
 /* GPM unit config (Gen9+) */
 #define CTC_MODE				_MMIO(0xa26c)
+#define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
 #define   CTC_SOURCE_PARAMETER_MASK		REG_BIT(0)
 #define   CTC_SOURCE_CRYSTAL_CLOCK		REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 0)
 #define   CTC_SOURCE_DIVIDE_LOGIC		REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 1)
-#define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
 
 /* GPM MSG_IDLE */
 #define MSG_IDLE_CS		_MMIO(0x8000)