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Ping-Ke ShihKalle Valo
Ping-Ke Shih
authored and
Kalle Valo
committed
rtw89: 8852c: add chip_ops related to BTC
Add some chip_ops to support BT coexistence to work properly. Signed-off-by: Ping-Ke Shih <[email protected]> Signed-off-by: Kalle Valo <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎drivers/net/wireless/realtek/rtw89/reg.h‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3048,11 +3048,18 @@
30483048
#define B_AX_BT_CNT_RST_V1 BIT(1)
30493049
#define B_AX_BT_CNT_EN BIT(0)
30503050

3051+
#define R_BTC_BT_CNT_HIGH 0xDA14
3052+
#define R_BTC_BT_CNT_LOW 0xDA18
3053+
30513054
#define R_AX_BTC_FUNC_EN 0xDA20
30523055
#define R_AX_BTC_FUNC_EN_C1 0xFA20
30533056
#define B_AX_PTA_WL_TX_EN BIT(1)
30543057
#define B_AX_PTA_EDCCA_EN BIT(0)
30553058

3059+
#define R_BTC_COEX_WL_REQ 0xDA24
3060+
#define B_BTC_TX_BCN_HI BIT(22)
3061+
#define B_BTC_RSP_ACK_HI BIT(10)
3062+
30563063
#define R_BTC_BREAK_TABLE 0xDA2C
30573064
#define BTC_BREAK_PARAM 0xf0ffffff
30583065

‎drivers/net/wireless/realtek/rtw89/rtw8852c.c‎

Lines changed: 187 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2338,6 +2338,33 @@ static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_p
23382338
return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
23392339
}
23402340

2341+
static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev)
2342+
{
2343+
struct rtw89_btc *btc = &rtwdev->btc;
2344+
struct rtw89_btc_module *module = &btc->mdinfo;
2345+
2346+
module->rfe_type = rtwdev->efuse.rfe_type;
2347+
module->cv = rtwdev->hal.cv;
2348+
module->bt_solo = 0;
2349+
module->switch_type = BTC_SWITCH_INTERNAL;
2350+
2351+
if (module->rfe_type > 0)
2352+
module->ant.num = (module->rfe_type % 2 ? 2 : 3);
2353+
else
2354+
module->ant.num = 2;
2355+
2356+
module->ant.diversity = 0;
2357+
module->ant.isolation = 10;
2358+
2359+
if (module->ant.num == 3) {
2360+
module->ant.type = BTC_ANT_DEDICATED;
2361+
module->bt_pos = BTC_BT_ALONE;
2362+
} else {
2363+
module->ant.type = BTC_ANT_SHARED;
2364+
module->bt_pos = BTC_BT_BTG;
2365+
}
2366+
}
2367+
23412368
static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
23422369
{
23432370
if (btg) {
@@ -2440,6 +2467,159 @@ static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev)
24402467
btc->cx.wl.status.map.init_ok = true;
24412468
}
24422469

2470+
static
2471+
void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2472+
{
2473+
u32 bitmap = 0;
2474+
u32 reg = 0;
2475+
2476+
switch (map) {
2477+
case BTC_PRI_MASK_TX_RESP:
2478+
reg = R_BTC_COEX_WL_REQ;
2479+
bitmap = B_BTC_RSP_ACK_HI;
2480+
break;
2481+
case BTC_PRI_MASK_BEACON:
2482+
reg = R_BTC_COEX_WL_REQ;
2483+
bitmap = B_BTC_TX_BCN_HI;
2484+
break;
2485+
default:
2486+
return;
2487+
}
2488+
2489+
if (state)
2490+
rtw89_write32_set(rtwdev, reg, bitmap);
2491+
else
2492+
rtw89_write32_clr(rtwdev, reg, bitmap);
2493+
}
2494+
2495+
union rtw8852c_btc_wl_txpwr_ctrl {
2496+
u32 txpwr_val;
2497+
struct {
2498+
union {
2499+
u16 ctrl_all_time;
2500+
struct {
2501+
s16 data:9;
2502+
u16 rsvd:6;
2503+
u16 flag:1;
2504+
} all_time;
2505+
};
2506+
union {
2507+
u16 ctrl_gnt_bt;
2508+
struct {
2509+
s16 data:9;
2510+
u16 rsvd:7;
2511+
} gnt_bt;
2512+
};
2513+
};
2514+
} __packed;
2515+
2516+
static void
2517+
rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2518+
{
2519+
union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2520+
s32 val;
2521+
2522+
#define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2523+
do { \
2524+
const typeof(_msk) __msk = _msk; \
2525+
const typeof(_en) __en = _en; \
2526+
u32 _wrt = FIELD_PREP(__msk, _val); \
2527+
BUILD_BUG_ON((__msk & __en) != 0); \
2528+
if (_cond) \
2529+
_wrt |= __en; \
2530+
else \
2531+
_wrt &= ~__en; \
2532+
rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2533+
__msk | __en, _wrt); \
2534+
} while (0)
2535+
2536+
switch (arg.ctrl_all_time) {
2537+
case 0xffff:
2538+
val = 0;
2539+
break;
2540+
default:
2541+
val = arg.all_time.data;
2542+
break;
2543+
}
2544+
2545+
__write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2546+
val, B_AX_FORCE_PWR_BY_RATE_EN,
2547+
arg.ctrl_all_time != 0xffff);
2548+
2549+
switch (arg.ctrl_gnt_bt) {
2550+
case 0xffff:
2551+
val = 0;
2552+
break;
2553+
default:
2554+
val = arg.gnt_bt.data;
2555+
break;
2556+
};
2557+
2558+
__write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2559+
B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2560+
2561+
#undef __write_ctrl
2562+
}
2563+
2564+
static
2565+
s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2566+
{
2567+
return clamp_t(s8, val, -100, 0) + 100;
2568+
}
2569+
2570+
static
2571+
void rtw8852c_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
2572+
{
2573+
struct rtw89_btc *btc = &rtwdev->btc;
2574+
struct rtw89_btc_dm *dm = &btc->dm;
2575+
struct rtw89_btc_bt_info *bt = &btc->cx.bt;
2576+
struct rtw89_btc_bt_link_info *b = &bt->link_info;
2577+
2578+
/* fix LNA2 = level-5 for BT ACI issue at BTG */
2579+
if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
2580+
dm->trx_para_level = 1;
2581+
}
2582+
2583+
static
2584+
void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2585+
{
2586+
struct rtw89_btc *btc = &rtwdev->btc;
2587+
struct rtw89_btc_cx *cx = &btc->cx;
2588+
u32 val;
2589+
2590+
val = rtw89_read32(rtwdev, R_BTC_BT_CNT_HIGH);
2591+
cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
2592+
cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
2593+
2594+
val = rtw89_read32(rtwdev, R_BTC_BT_CNT_LOW);
2595+
cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
2596+
cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
2597+
2598+
/* clock-gate off before reset counter*/
2599+
rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
2600+
rtw89_write32_clr(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_RST);
2601+
rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_RST);
2602+
rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
2603+
}
2604+
2605+
static
2606+
void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2607+
{
2608+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2609+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2610+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620);
2611+
2612+
/* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2613+
if (state)
2614+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2615+
RFREG_MASK, 0x179c);
2616+
else
2617+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2618+
RFREG_MASK, 0x208);
2619+
2620+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2621+
}
2622+
24432623
static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
24442624
struct rtw89_rx_phy_ppdu *phy_ppdu,
24452625
struct ieee80211_rx_status *status)
@@ -2546,7 +2726,14 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = {
25462726
.resume_sch_tx = rtw89_mac_resume_sch_tx_v1,
25472727
.h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1,
25482728

2729+
.btc_set_rfe = rtw8852c_btc_set_rfe,
25492730
.btc_init_cfg = rtw8852c_btc_init_cfg,
2731+
.btc_set_wl_pri = rtw8852c_btc_set_wl_pri,
2732+
.btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl,
2733+
.btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi,
2734+
.btc_bt_aci_imp = rtw8852c_btc_bt_aci_imp,
2735+
.btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt,
2736+
.btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby,
25502737
};
25512738

25522739
const struct rtw89_chip_info rtw8852c_chip_info = {

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