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Merge tag 'net-6.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Pull networking fixes from Paolo Abeni: "Including fixes from bluetooth. Current release - new code bugs: - netfilter: complete validation of user input - mlx5: disallow SRIOV switchdev mode when in multi-PF netdev Previous releases - regressions: - core: fix u64_stats_init() for lockdep when used repeatedly in one file - ipv6: fix race condition between ipv6_get_ifaddr and ipv6_del_addr - bluetooth: fix memory leak in hci_req_sync_complete() - batman-adv: avoid infinite loop trying to resize local TT - drv: geneve: fix header validation in geneve[6]_xmit_skb - drv: bnxt_en: fix possible memory leak in bnxt_rdma_aux_device_init() - drv: mlx5: offset comp irq index in name by one - drv: ena: avoid double-free clearing stale tx_info->xdpf value - drv: pds_core: fix pdsc_check_pci_health deadlock Previous releases - always broken: - xsk: validate user input for XDP_{UMEM|COMPLETION}_FILL_RING - bluetooth: fix setsockopt not validating user input - af_unix: clear stale u->oob_skb. - nfc: llcp: fix nfc_llcp_setsockopt() unsafe copies - drv: virtio_net: fix guest hangup on invalid RSS update - drv: mlx5e: Fix mlx5e_priv_init() cleanup flow - dsa: mt7530: trap link-local frames regardless of ST Port State" * tag 'net-6.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (59 commits) net: ena: Set tx_info->xdpf value to NULL net: ena: Fix incorrect descriptor free behavior net: ena: Wrong missing IO completions check order net: ena: Fix potential sign extension issue af_unix: Fix garbage collector racing against connect() net: dsa: mt7530: trap link-local frames regardless of ST Port State Revert "s390/ism: fix receive message buffer allocation" net: sparx5: fix wrong config being used when reconfiguring PCS net/mlx5: fix possible stack overflows net/mlx5: Disallow SRIOV switchdev mode when in multi-PF netdev net/mlx5e: RSS, Block XOR hash with over 128 channels net/mlx5e: Do not produce metadata freelist entries in Tx port ts WQE xmit net/mlx5e: HTB, Fix inconsistencies with QoS SQs number net/mlx5e: Fix mlx5e_priv_init() cleanup flow net/mlx5e: RSS, Block changing channels number when RXFH is configured net/mlx5: Correctly compare pkt reformat ids net/mlx5: Properly link new fs rules into the tree net/mlx5: offset comp irq index in name by one net/mlx5: Register devlink first under devlink lock net/mlx5: E-switch, store eswitch pointer before registering devlink_param ...
2 parents ab4319f + 4e1ad31 commit 2ae9a89

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MAINTAINERS

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2191,7 +2191,6 @@ N: mxs
21912191

21922192
ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE
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M: Shawn Guo <[email protected]>
2194-
M: Li Yang <[email protected]>
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L: [email protected] (moderated for non-subscribers)
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S: Maintained
21972196
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
@@ -8524,7 +8523,6 @@ S: Maintained
85248523
F: drivers/video/fbdev/fsl-diu-fb.*
85258524

85268525
FREESCALE DMA DRIVER
8527-
M: Li Yang <[email protected]>
85288526
M: Zhang Wei <[email protected]>
85298527
85308528
S: Maintained
@@ -8689,10 +8687,9 @@ F: drivers/soc/fsl/qe/tsa.h
86898687
F: include/dt-bindings/soc/cpm1-fsl,tsa.h
86908688

86918689
FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
8692-
M: Li Yang <[email protected]>
86938690
86948691
8695-
S: Maintained
8692+
S: Orphan
86968693
F: drivers/net/ethernet/freescale/ucc_geth*
86978694

86988695
FREESCALE QUICC ENGINE UCC HDLC DRIVER
@@ -8709,10 +8706,9 @@ S: Maintained
87098706
F: drivers/tty/serial/ucc_uart.c
87108707

87118708
FREESCALE SOC DRIVERS
8712-
M: Li Yang <[email protected]>
87138709
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L: [email protected] (moderated for non-subscribers)
8715-
S: Maintained
8711+
S: Orphan
87168712
F: Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml
87178713
F: Documentation/devicetree/bindings/soc/fsl/
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F: drivers/soc/fsl/
@@ -8746,10 +8742,9 @@ F: Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
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F: sound/soc/fsl/fsl_qmc_audio.c
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87488744
FREESCALE USB PERIPHERAL DRIVERS
8749-
M: Li Yang <[email protected]>
87508745
87518746
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S: Maintained
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S: Orphan
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F: drivers/usb/gadget/udc/fsl*
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FREESCALE USB PHY DRIVER

drivers/isdn/mISDN/socket.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -401,23 +401,23 @@ data_sock_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg)
401401
}
402402

403403
static int data_sock_setsockopt(struct socket *sock, int level, int optname,
404-
sockptr_t optval, unsigned int len)
404+
sockptr_t optval, unsigned int optlen)
405405
{
406406
struct sock *sk = sock->sk;
407407
int err = 0, opt = 0;
408408

409409
if (*debug & DEBUG_SOCKET)
410410
printk(KERN_DEBUG "%s(%p, %d, %x, optval, %d)\n", __func__, sock,
411-
level, optname, len);
411+
level, optname, optlen);
412412

413413
lock_sock(sk);
414414

415415
switch (optname) {
416416
case MISDN_TIME_STAMP:
417-
if (copy_from_sockptr(&opt, optval, sizeof(int))) {
418-
err = -EFAULT;
417+
err = copy_safe_from_sockptr(&opt, sizeof(opt),
418+
optval, optlen);
419+
if (err)
419420
break;
420-
}
421421

422422
if (opt)
423423
_pms(sk)->cmask |= MISDN_TIME_STAMP;

drivers/net/dsa/mt7530.c

Lines changed: 207 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -950,56 +950,217 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
950950
mutex_unlock(&priv->reg_mutex);
951951
}
952952

953-
/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
954-
* 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
955-
* must only be propagated to C-VLAN and MAC Bridge components. That means
956-
* VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
957-
* these frames are supposed to be processed by the CPU (software). So we make
958-
* the switch only forward them to the CPU port. And if received from a CPU
959-
* port, forward to a single port. The software is responsible of making the
960-
* switch conform to the latter by setting a single port as destination port on
961-
* the special tag.
953+
/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
954+
* of the Open Systems Interconnection basic reference model (OSI/RM) are
955+
* described; the medium access control (MAC) and logical link control (LLC)
956+
* sublayers. The MAC sublayer is the one facing the physical layer.
962957
*
963-
* This switch intellectual property cannot conform to this part of the standard
964-
* fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
965-
* DAs, it also includes :22-FF which the scope of propagation is not supposed
966-
* to be restricted for these MAC DAs.
958+
* In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
959+
* Bridge component comprises a MAC Relay Entity for interconnecting the Ports
960+
* of the Bridge, at least two Ports, and higher layer entities with at least a
961+
* Spanning Tree Protocol Entity included.
962+
*
963+
* Each Bridge Port also functions as an end station and shall provide the MAC
964+
* Service to an LLC Entity. Each instance of the MAC Service is provided to a
965+
* distinct LLC Entity that supports protocol identification, multiplexing, and
966+
* demultiplexing, for protocol data unit (PDU) transmission and reception by
967+
* one or more higher layer entities.
968+
*
969+
* It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
970+
* Entity associated with each Bridge Port is modeled as being directly
971+
* connected to the attached Local Area Network (LAN).
972+
*
973+
* On the switch with CPU port architecture, CPU port functions as Management
974+
* Port, and the Management Port functionality is provided by software which
975+
* functions as an end station. Software is connected to an IEEE 802 LAN that is
976+
* wholly contained within the system that incorporates the Bridge. Software
977+
* provides access to the LLC Entity associated with each Bridge Port by the
978+
* value of the source port field on the special tag on the frame received by
979+
* software.
980+
*
981+
* We call frames that carry control information to determine the active
982+
* topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
983+
* spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
984+
* Protocol Data Units (MVRPDUs), and frames from other link constrained
985+
* protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
986+
* Link Layer Discovery Protocol (LLDP), link-local frames. They are not
987+
* forwarded by a Bridge. Permanently configured entries in the filtering
988+
* database (FDB) ensure that such frames are discarded by the Forwarding
989+
* Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
990+
*
991+
* Each of the reserved MAC addresses specified in Table 8-1
992+
* (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
993+
* permanently configured in the FDB in C-VLAN components and ERs.
994+
*
995+
* Each of the reserved MAC addresses specified in Table 8-2
996+
* (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
997+
* configured in the FDB in S-VLAN components.
998+
*
999+
* Each of the reserved MAC addresses specified in Table 8-3
1000+
* (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
1001+
* TPMR components.
1002+
*
1003+
* The FDB entries for reserved MAC addresses shall specify filtering for all
1004+
* Bridge Ports and all VIDs. Management shall not provide the capability to
1005+
* modify or remove entries for reserved MAC addresses.
1006+
*
1007+
* The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
1008+
* propagation of PDUs within a Bridged Network, as follows:
1009+
*
1010+
* The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
1011+
* conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
1012+
* component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
1013+
* PDUs transmitted using this destination address, or any other addresses
1014+
* that appear in Table 8-1, Table 8-2, and Table 8-3
1015+
* (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
1016+
* therefore travel no further than those stations that can be reached via a
1017+
* single individual LAN from the originating station.
1018+
*
1019+
* The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
1020+
* address that no conformant S-VLAN component, C-VLAN component, or MAC
1021+
* Bridge can forward; however, this address is relayed by a TPMR component.
1022+
* PDUs using this destination address, or any of the other addresses that
1023+
* appear in both Table 8-1 and Table 8-2 but not in Table 8-3
1024+
* (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
1025+
* any TPMRs but will propagate no further than the nearest S-VLAN component,
1026+
* C-VLAN component, or MAC Bridge.
1027+
*
1028+
* The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
1029+
* that no conformant C-VLAN component, MAC Bridge can forward; however, it is
1030+
* relayed by TPMR components and S-VLAN components. PDUs using this
1031+
* destination address, or any of the other addresses that appear in Table 8-1
1032+
* but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
1033+
* will be relayed by TPMR components and S-VLAN components but will propagate
1034+
* no further than the nearest C-VLAN component or MAC Bridge.
1035+
*
1036+
* Because the LLC Entity associated with each Bridge Port is provided via CPU
1037+
* port, we must not filter these frames but forward them to CPU port.
1038+
*
1039+
* In a Bridge, the transmission Port is majorly decided by ingress and egress
1040+
* rules, FDB, and spanning tree Port State functions of the Forwarding Process.
1041+
* For link-local frames, only CPU port should be designated as destination port
1042+
* in the FDB, and the other functions of the Forwarding Process must not
1043+
* interfere with the decision of the transmission Port. We call this process
1044+
* trapping frames to CPU port.
1045+
*
1046+
* Therefore, on the switch with CPU port architecture, link-local frames must
1047+
* be trapped to CPU port, and certain link-local frames received by a Port of a
1048+
* Bridge comprising a TPMR component or an S-VLAN component must be excluded
1049+
* from it.
1050+
*
1051+
* A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
1052+
* MAC Relay (TPMR) component as a TPMR component supports only a subset of the
1053+
* functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
1054+
* doesn't count) of this architecture will either function as a standard MAC
1055+
* Bridge or a standard VLAN Bridge.
1056+
*
1057+
* Therefore, a Bridge of this architecture can only comprise S-VLAN components,
1058+
* C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
1059+
* we don't need to relay PDUs using the destination addresses specified on the
1060+
* Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
1061+
* section where they must be relayed by TPMR components.
1062+
*
1063+
* One option to trap link-local frames to CPU port is to add static FDB entries
1064+
* with CPU port designated as destination port. However, because that
1065+
* Independent VLAN Learning (IVL) is being used on every VID, each entry only
1066+
* applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
1067+
* Bridge component or a C-VLAN component, there would have to be 16 times 4096
1068+
* entries. This switch intellectual property can only hold a maximum of 2048
1069+
* entries. Using this option, there also isn't a mechanism to prevent
1070+
* link-local frames from being discarded when the spanning tree Port State of
1071+
* the reception Port is discarding.
1072+
*
1073+
* The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
1074+
* registers. Whilst this applies to every VID, it doesn't contain all of the
1075+
* reserved MAC addresses without affecting the remaining Standard Group MAC
1076+
* Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
1077+
* remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
1078+
* addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
1079+
* destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
1080+
* The latter option provides better but not complete conformance.
1081+
*
1082+
* This switch intellectual property also does not provide a mechanism to trap
1083+
* link-local frames with specific destination addresses to CPU port by Bridge,
1084+
* to conform to the filtering rules for the distinct Bridge components.
1085+
*
1086+
* Therefore, regardless of the type of the Bridge component, link-local frames
1087+
* with these destination addresses will be trapped to CPU port:
1088+
*
1089+
* 01-80-C2-00-00-[00,01,02,03,0E]
1090+
*
1091+
* In a Bridge comprising a MAC Bridge component or a C-VLAN component:
1092+
*
1093+
* Link-local frames with these destination addresses won't be trapped to CPU
1094+
* port which won't conform to IEEE Std 802.1Q-2022:
1095+
*
1096+
* 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
1097+
*
1098+
* In a Bridge comprising an S-VLAN component:
1099+
*
1100+
* Link-local frames with these destination addresses will be trapped to CPU
1101+
* port which won't conform to IEEE Std 802.1Q-2022:
1102+
*
1103+
* 01-80-C2-00-00-00
1104+
*
1105+
* Link-local frames with these destination addresses won't be trapped to CPU
1106+
* port which won't conform to IEEE Std 802.1Q-2022:
1107+
*
1108+
* 01-80-C2-00-00-[04,05,06,07,08,09,0A]
1109+
*
1110+
* To trap link-local frames to CPU port as conformant as this switch
1111+
* intellectual property can allow, link-local frames are made to be regarded as
1112+
* Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
1113+
* property only lets the frames regarded as BPDUs bypass the spanning tree Port
1114+
* State function of the Forwarding Process.
1115+
*
1116+
* The only remaining interference is the ingress rules. When the reception Port
1117+
* has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
1118+
* There doesn't seem to be a mechanism on the switch intellectual property to
1119+
* have link-local frames bypass this function of the Forwarding Process.
9671120
*/
9681121
static void
9691122
mt753x_trap_frames(struct mt7530_priv *priv)
9701123
{
9711124
/* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them
9721125
* VLAN-untagged.
9731126
*/
974-
mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK |
975-
MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
976-
MT753X_BPDU_PORT_FW_MASK,
977-
MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
978-
MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
979-
MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
980-
MT753X_BPDU_CPU_ONLY);
1127+
mt7530_rmw(priv, MT753X_BPC,
1128+
MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
1129+
MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
1130+
MT753X_BPDU_PORT_FW_MASK,
1131+
MT753X_PAE_BPDU_FR |
1132+
MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1133+
MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
1134+
MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1135+
MT753X_BPDU_CPU_ONLY);
9811136

9821137
/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
9831138
* them VLAN-untagged.
9841139
*/
985-
mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |
986-
MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
987-
MT753X_R01_PORT_FW_MASK,
988-
MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
989-
MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
990-
MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
991-
MT753X_BPDU_CPU_ONLY);
1140+
mt7530_rmw(priv, MT753X_RGAC1,
1141+
MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
1142+
MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
1143+
MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
1144+
MT753X_R02_BPDU_FR |
1145+
MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1146+
MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
1147+
MT753X_R01_BPDU_FR |
1148+
MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1149+
MT753X_BPDU_CPU_ONLY);
9921150

9931151
/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
9941152
* them VLAN-untagged.
9951153
*/
996-
mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |
997-
MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
998-
MT753X_R03_PORT_FW_MASK,
999-
MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1000-
MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
1001-
MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1002-
MT753X_BPDU_CPU_ONLY);
1154+
mt7530_rmw(priv, MT753X_RGAC2,
1155+
MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
1156+
MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
1157+
MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
1158+
MT753X_R0E_BPDU_FR |
1159+
MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1160+
MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
1161+
MT753X_R03_BPDU_FR |
1162+
MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1163+
MT753X_BPDU_CPU_ONLY);
10031164
}
10041165

10051166
static void
@@ -2505,18 +2666,25 @@ mt7531_setup(struct dsa_switch *ds)
25052666
mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
25062667
MT7531_GPIO0_INTERRUPT);
25072668

2508-
/* Enable PHY core PLL, since phy_device has not yet been created
2509-
* provided for phy_[read,write]_mmd_indirect is called, we provide
2510-
* our own mt7531_ind_mmd_phy_[read,write] to complete this
2511-
* function.
2669+
/* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
2670+
* phy_device has not yet been created provided for
2671+
* phy_[read,write]_mmd_indirect is called, we provide our own
2672+
* mt7531_ind_mmd_phy_[read,write] to complete this function.
25122673
*/
25132674
val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
25142675
MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2515-
val |= MT7531_PHY_PLL_BYPASS_MODE;
2676+
val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
25162677
val &= ~MT7531_PHY_PLL_OFF;
25172678
mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
25182679
CORE_PLL_GROUP4, val);
25192680

2681+
/* Disable EEE advertisement on the switch PHYs. */
2682+
for (i = MT753X_CTRL_PHY_ADDR;
2683+
i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
2684+
mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
2685+
0);
2686+
}
2687+
25202688
mt7531_setup_common(ds);
25212689

25222690
/* Setup VLAN ID 0 for VLAN-unaware bridges */

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