@@ -950,56 +950,217 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
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mutex_unlock (& priv -> reg_mutex );
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}
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- /* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
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- * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
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- * must only be propagated to C-VLAN and MAC Bridge components. That means
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- * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
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- * these frames are supposed to be processed by the CPU (software). So we make
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- * the switch only forward them to the CPU port. And if received from a CPU
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- * port, forward to a single port. The software is responsible of making the
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- * switch conform to the latter by setting a single port as destination port on
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- * the special tag.
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+ /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
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+ * of the Open Systems Interconnection basic reference model (OSI/RM) are
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+ * described; the medium access control (MAC) and logical link control (LLC)
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+ * sublayers. The MAC sublayer is the one facing the physical layer.
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*
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- * This switch intellectual property cannot conform to this part of the standard
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- * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
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- * DAs, it also includes :22-FF which the scope of propagation is not supposed
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- * to be restricted for these MAC DAs.
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+ * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
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+ * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
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+ * of the Bridge, at least two Ports, and higher layer entities with at least a
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+ * Spanning Tree Protocol Entity included.
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+ *
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+ * Each Bridge Port also functions as an end station and shall provide the MAC
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+ * Service to an LLC Entity. Each instance of the MAC Service is provided to a
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+ * distinct LLC Entity that supports protocol identification, multiplexing, and
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+ * demultiplexing, for protocol data unit (PDU) transmission and reception by
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+ * one or more higher layer entities.
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+ *
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+ * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
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+ * Entity associated with each Bridge Port is modeled as being directly
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+ * connected to the attached Local Area Network (LAN).
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+ *
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+ * On the switch with CPU port architecture, CPU port functions as Management
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+ * Port, and the Management Port functionality is provided by software which
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+ * functions as an end station. Software is connected to an IEEE 802 LAN that is
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+ * wholly contained within the system that incorporates the Bridge. Software
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+ * provides access to the LLC Entity associated with each Bridge Port by the
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+ * value of the source port field on the special tag on the frame received by
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+ * software.
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+ *
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+ * We call frames that carry control information to determine the active
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+ * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
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+ * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
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+ * Protocol Data Units (MVRPDUs), and frames from other link constrained
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+ * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
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+ * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
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+ * forwarded by a Bridge. Permanently configured entries in the filtering
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+ * database (FDB) ensure that such frames are discarded by the Forwarding
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+ * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
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+ *
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+ * Each of the reserved MAC addresses specified in Table 8-1
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+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
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+ * permanently configured in the FDB in C-VLAN components and ERs.
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+ *
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+ * Each of the reserved MAC addresses specified in Table 8-2
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+ * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
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+ * configured in the FDB in S-VLAN components.
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+ *
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+ * Each of the reserved MAC addresses specified in Table 8-3
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+ * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
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+ * TPMR components.
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+ *
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+ * The FDB entries for reserved MAC addresses shall specify filtering for all
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+ * Bridge Ports and all VIDs. Management shall not provide the capability to
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+ * modify or remove entries for reserved MAC addresses.
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+ *
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+ * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
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+ * propagation of PDUs within a Bridged Network, as follows:
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+ *
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+ * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
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+ * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
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+ * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
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+ * PDUs transmitted using this destination address, or any other addresses
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+ * that appear in Table 8-1, Table 8-2, and Table 8-3
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+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
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+ * therefore travel no further than those stations that can be reached via a
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+ * single individual LAN from the originating station.
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+ *
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+ * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
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+ * address that no conformant S-VLAN component, C-VLAN component, or MAC
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+ * Bridge can forward; however, this address is relayed by a TPMR component.
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+ * PDUs using this destination address, or any of the other addresses that
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+ * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
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+ * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
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+ * any TPMRs but will propagate no further than the nearest S-VLAN component,
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+ * C-VLAN component, or MAC Bridge.
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+ *
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+ * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
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+ * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
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+ * relayed by TPMR components and S-VLAN components. PDUs using this
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+ * destination address, or any of the other addresses that appear in Table 8-1
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+ * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
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+ * will be relayed by TPMR components and S-VLAN components but will propagate
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+ * no further than the nearest C-VLAN component or MAC Bridge.
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+ *
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+ * Because the LLC Entity associated with each Bridge Port is provided via CPU
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+ * port, we must not filter these frames but forward them to CPU port.
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+ *
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+ * In a Bridge, the transmission Port is majorly decided by ingress and egress
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+ * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
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+ * For link-local frames, only CPU port should be designated as destination port
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+ * in the FDB, and the other functions of the Forwarding Process must not
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+ * interfere with the decision of the transmission Port. We call this process
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+ * trapping frames to CPU port.
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+ *
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+ * Therefore, on the switch with CPU port architecture, link-local frames must
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+ * be trapped to CPU port, and certain link-local frames received by a Port of a
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+ * Bridge comprising a TPMR component or an S-VLAN component must be excluded
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+ * from it.
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+ *
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+ * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
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+ * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
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+ * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
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+ * doesn't count) of this architecture will either function as a standard MAC
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+ * Bridge or a standard VLAN Bridge.
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+ *
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+ * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
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+ * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
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+ * we don't need to relay PDUs using the destination addresses specified on the
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+ * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
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+ * section where they must be relayed by TPMR components.
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+ *
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+ * One option to trap link-local frames to CPU port is to add static FDB entries
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+ * with CPU port designated as destination port. However, because that
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+ * Independent VLAN Learning (IVL) is being used on every VID, each entry only
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+ * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
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+ * Bridge component or a C-VLAN component, there would have to be 16 times 4096
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+ * entries. This switch intellectual property can only hold a maximum of 2048
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+ * entries. Using this option, there also isn't a mechanism to prevent
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+ * link-local frames from being discarded when the spanning tree Port State of
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+ * the reception Port is discarding.
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+ *
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+ * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
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+ * registers. Whilst this applies to every VID, it doesn't contain all of the
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+ * reserved MAC addresses without affecting the remaining Standard Group MAC
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+ * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
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+ * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
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+ * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
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+ * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
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+ * The latter option provides better but not complete conformance.
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+ *
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+ * This switch intellectual property also does not provide a mechanism to trap
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+ * link-local frames with specific destination addresses to CPU port by Bridge,
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+ * to conform to the filtering rules for the distinct Bridge components.
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+ *
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+ * Therefore, regardless of the type of the Bridge component, link-local frames
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+ * with these destination addresses will be trapped to CPU port:
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+ *
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+ * 01-80-C2-00-00-[00,01,02,03,0E]
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+ *
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+ * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
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+ *
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+ * Link-local frames with these destination addresses won't be trapped to CPU
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+ * port which won't conform to IEEE Std 802.1Q-2022:
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+ *
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+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
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+ *
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+ * In a Bridge comprising an S-VLAN component:
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+ *
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+ * Link-local frames with these destination addresses will be trapped to CPU
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+ * port which won't conform to IEEE Std 802.1Q-2022:
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+ *
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+ * 01-80-C2-00-00-00
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+ *
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+ * Link-local frames with these destination addresses won't be trapped to CPU
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+ * port which won't conform to IEEE Std 802.1Q-2022:
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+ *
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+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
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+ *
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+ * To trap link-local frames to CPU port as conformant as this switch
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+ * intellectual property can allow, link-local frames are made to be regarded as
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+ * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
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+ * property only lets the frames regarded as BPDUs bypass the spanning tree Port
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+ * State function of the Forwarding Process.
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+ *
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+ * The only remaining interference is the ingress rules. When the reception Port
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+ * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
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+ * There doesn't seem to be a mechanism on the switch intellectual property to
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+ * have link-local frames bypass this function of the Forwarding Process.
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*/
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static void
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mt753x_trap_frames (struct mt7530_priv * priv )
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{
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/* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them
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* VLAN-untagged.
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*/
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- mt7530_rmw (priv , MT753X_BPC , MT753X_PAE_EG_TAG_MASK |
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- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
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- MT753X_BPDU_PORT_FW_MASK ,
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- MT753X_PAE_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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- MT753X_PAE_PORT_FW (MT753X_BPDU_CPU_ONLY ) |
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- MT753X_BPDU_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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- MT753X_BPDU_CPU_ONLY );
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+ mt7530_rmw (priv , MT753X_BPC ,
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+ MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
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+ MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
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+ MT753X_BPDU_PORT_FW_MASK ,
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+ MT753X_PAE_BPDU_FR |
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+ MT753X_PAE_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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+ MT753X_PAE_PORT_FW (MT753X_BPDU_CPU_ONLY ) |
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+ MT753X_BPDU_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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+ MT753X_BPDU_CPU_ONLY );
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/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
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* them VLAN-untagged.
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*/
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- mt7530_rmw (priv , MT753X_RGAC1 , MT753X_R02_EG_TAG_MASK |
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- MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
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- MT753X_R01_PORT_FW_MASK ,
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- MT753X_R02_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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- MT753X_R02_PORT_FW (MT753X_BPDU_CPU_ONLY ) |
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- MT753X_R01_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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- MT753X_BPDU_CPU_ONLY );
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+ mt7530_rmw (priv , MT753X_RGAC1 ,
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+ MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
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+ MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
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+ MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK ,
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+ MT753X_R02_BPDU_FR |
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+ MT753X_R02_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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+ MT753X_R02_PORT_FW (MT753X_BPDU_CPU_ONLY ) |
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+ MT753X_R01_BPDU_FR |
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+ MT753X_R01_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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+ MT753X_BPDU_CPU_ONLY );
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/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
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* them VLAN-untagged.
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*/
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- mt7530_rmw (priv , MT753X_RGAC2 , MT753X_R0E_EG_TAG_MASK |
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- MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
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- MT753X_R03_PORT_FW_MASK ,
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- MT753X_R0E_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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- MT753X_R0E_PORT_FW (MT753X_BPDU_CPU_ONLY ) |
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- MT753X_R03_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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- MT753X_BPDU_CPU_ONLY );
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+ mt7530_rmw (priv , MT753X_RGAC2 ,
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+ MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
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+ MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
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+ MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK ,
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+ MT753X_R0E_BPDU_FR |
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+ MT753X_R0E_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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+ MT753X_R0E_PORT_FW (MT753X_BPDU_CPU_ONLY ) |
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+ MT753X_R03_BPDU_FR |
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+ MT753X_R03_EG_TAG (MT7530_VLAN_EG_UNTAGGED ) |
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+ MT753X_BPDU_CPU_ONLY );
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}
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static void
@@ -2505,18 +2666,25 @@ mt7531_setup(struct dsa_switch *ds)
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mt7530_rmw (priv , MT7531_GPIO_MODE0 , MT7531_GPIO0_MASK ,
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MT7531_GPIO0_INTERRUPT );
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- /* Enable PHY core PLL, since phy_device has not yet been created
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- * provided for phy_[read,write]_mmd_indirect is called, we provide
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- * our own mt7531_ind_mmd_phy_ [read,write] to complete this
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- * function.
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+ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
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+ * phy_device has not yet been created provided for
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+ * phy_ [read,write]_mmd_indirect is called, we provide our own
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+ * mt7531_ind_mmd_phy_[read,write] to complete this function.
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*/
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val = mt7531_ind_c45_phy_read (priv , MT753X_CTRL_PHY_ADDR ,
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MDIO_MMD_VEND2 , CORE_PLL_GROUP4 );
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- val |= MT7531_PHY_PLL_BYPASS_MODE ;
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+ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE ;
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val &= ~MT7531_PHY_PLL_OFF ;
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mt7531_ind_c45_phy_write (priv , MT753X_CTRL_PHY_ADDR , MDIO_MMD_VEND2 ,
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CORE_PLL_GROUP4 , val );
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+ /* Disable EEE advertisement on the switch PHYs. */
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+ for (i = MT753X_CTRL_PHY_ADDR ;
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+ i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS ; i ++ ) {
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+ mt7531_ind_c45_phy_write (priv , i , MDIO_MMD_AN , MDIO_AN_EEE_ADV ,
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+ 0 );
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+ }
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+
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mt7531_setup_common (ds );
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/* Setup VLAN ID 0 for VLAN-unaware bridges */
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