Skip to content

Commit 16438b6

Browse files
ilkka-koskinenacmel
ilkka-koskinen
authored and
acmel
committed
perf vendor events arm64 AmpereOneX: Add core PMU events and metrics
Add JSON files for AmpereOneX core PMU events and metrics. Reviewed-by: Ian Rogers <[email protected]> Signed-off-by: Ilkka Koskinen <[email protected]> Cc: Adrian Hunter <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: James Clark <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: John Garry <[email protected]> Cc: Leo Yan <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Mike Leach <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Will Deacon <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
1 parent 10a149e commit 16438b6

File tree

13 files changed

+1713
-0
lines changed

13 files changed

+1713
-0
lines changed

‎tools/perf/pmu-events/arch/arm64/ampere/ampereonex/branch.json‎

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
1+
[
2+
{
3+
"ArchStdEvent": "BR_IMMED_SPEC"
4+
},
5+
{
6+
"ArchStdEvent": "BR_RETURN_SPEC"
7+
},
8+
{
9+
"ArchStdEvent": "BR_INDIRECT_SPEC"
10+
},
11+
{
12+
"ArchStdEvent": "BR_MIS_PRED"
13+
},
14+
{
15+
"ArchStdEvent": "BR_PRED"
16+
},
17+
{
18+
"PublicDescription": "Instruction architecturally executed, branch not taken",
19+
"EventCode": "0x8107",
20+
"EventName": "BR_SKIP_RETIRED",
21+
"BriefDescription": "Instruction architecturally executed, branch not taken"
22+
},
23+
{
24+
"PublicDescription": "Instruction architecturally executed, immediate branch taken",
25+
"EventCode": "0x8108",
26+
"EventName": "BR_IMMED_TAKEN_RETIRED",
27+
"BriefDescription": "Instruction architecturally executed, immediate branch taken"
28+
},
29+
{
30+
"PublicDescription": "Instruction architecturally executed, indirect branch excluding return retired",
31+
"EventCode": "0x810c",
32+
"EventName": "BR_INDNR_TAKEN_RETIRED",
33+
"BriefDescription": "Instruction architecturally executed, indirect branch excluding return retired"
34+
},
35+
{
36+
"PublicDescription": "Instruction architecturally executed, predicted immediate branch",
37+
"EventCode": "0x8110",
38+
"EventName": "BR_IMMED_PRED_RETIRED",
39+
"BriefDescription": "Instruction architecturally executed, predicted immediate branch"
40+
},
41+
{
42+
"PublicDescription": "Instruction architecturally executed, mispredicted immediate branch",
43+
"EventCode": "0x8111",
44+
"EventName": "BR_IMMED_MIS_PRED_RETIRED",
45+
"BriefDescription": "Instruction architecturally executed, mispredicted immediate branch"
46+
},
47+
{
48+
"PublicDescription": "Instruction architecturally executed, predicted indirect branch",
49+
"EventCode": "0x8112",
50+
"EventName": "BR_IND_PRED_RETIRED",
51+
"BriefDescription": "Instruction architecturally executed, predicted indirect branch"
52+
},
53+
{
54+
"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch",
55+
"EventCode": "0x8113",
56+
"EventName": "BR_IND_MIS_PRED_RETIRED",
57+
"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch"
58+
},
59+
{
60+
"PublicDescription": "Instruction architecturally executed, predicted procedure return",
61+
"EventCode": "0x8114",
62+
"EventName": "BR_RETURN_PRED_RETIRED",
63+
"BriefDescription": "Instruction architecturally executed, predicted procedure return"
64+
},
65+
{
66+
"PublicDescription": "Instruction architecturally executed, mispredicted procedure return",
67+
"EventCode": "0x8115",
68+
"EventName": "BR_RETURN_MIS_PRED_RETIRED",
69+
"BriefDescription": "Instruction architecturally executed, mispredicted procedure return"
70+
},
71+
{
72+
"PublicDescription": "Instruction architecturally executed, predicted indirect branch excluding return",
73+
"EventCode": "0x8116",
74+
"EventName": "BR_INDNR_PRED_RETIRED",
75+
"BriefDescription": "Instruction architecturally executed, predicted indirect branch excluding return"
76+
},
77+
{
78+
"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return",
79+
"EventCode": "0x8117",
80+
"EventName": "BR_INDNR_MIS_PRED_RETIRED",
81+
"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return"
82+
},
83+
{
84+
"PublicDescription": "Instruction architecturally executed, predicted branch, taken",
85+
"EventCode": "0x8118",
86+
"EventName": "BR_TAKEN_PRED_RETIRED",
87+
"BriefDescription": "Instruction architecturally executed, predicted branch, taken"
88+
},
89+
{
90+
"PublicDescription": "Instruction architecturally executed, mispredicted branch, taken",
91+
"EventCode": "0x8119",
92+
"EventName": "BR_TAKEN_MIS_PRED_RETIRED",
93+
"BriefDescription": "Instruction architecturally executed, mispredicted branch, taken"
94+
},
95+
{
96+
"PublicDescription": "Instruction architecturally executed, predicted branch, not taken",
97+
"EventCode": "0x811a",
98+
"EventName": "BR_SKIP_PRED_RETIRED",
99+
"BriefDescription": "Instruction architecturally executed, predicted branch, not taken"
100+
},
101+
{
102+
"PublicDescription": "Instruction architecturally executed, mispredicted branch, not taken",
103+
"EventCode": "0x811b",
104+
"EventName": "BR_SKIP_MIS_PRED_RETIRED",
105+
"BriefDescription": "Instruction architecturally executed, mispredicted branch, not taken"
106+
},
107+
{
108+
"PublicDescription": "Instruction architecturally executed, predicted branch",
109+
"EventCode": "0x811c",
110+
"EventName": "BR_PRED_RETIRED",
111+
"BriefDescription": "Instruction architecturally executed, predicted branch"
112+
},
113+
{
114+
"PublicDescription": "Instruction architecturally executed, indirect branch",
115+
"EventCode": "0x811d",
116+
"EventName": "BR_IND_RETIRED",
117+
"BriefDescription": "Instruction architecturally executed, indirect branch"
118+
},
119+
{
120+
"PublicDescription": "Branch Record captured.",
121+
"EventCode": "0x811f",
122+
"EventName": "BRB_FILTRATE",
123+
"BriefDescription": "Branch Record captured."
124+
}
125+
]

‎tools/perf/pmu-events/arch/arm64/ampere/ampereonex/bus.json‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
[
2+
{
3+
"ArchStdEvent": "CPU_CYCLES"
4+
},
5+
{
6+
"ArchStdEvent": "BUS_CYCLES"
7+
},
8+
{
9+
"ArchStdEvent": "BUS_ACCESS_RD"
10+
},
11+
{
12+
"ArchStdEvent": "BUS_ACCESS_WR"
13+
},
14+
{
15+
"ArchStdEvent": "BUS_ACCESS"
16+
},
17+
{
18+
"ArchStdEvent": "CNT_CYCLES"
19+
}
20+
]

‎tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json‎

Lines changed: 206 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,206 @@
1+
[
2+
{
3+
"ArchStdEvent": "L1D_CACHE_RD"
4+
},
5+
{
6+
"ArchStdEvent": "L1D_CACHE_WR"
7+
},
8+
{
9+
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
10+
},
11+
{
12+
"ArchStdEvent": "L1D_CACHE_INVAL"
13+
},
14+
{
15+
"ArchStdEvent": "L1D_TLB_REFILL_RD"
16+
},
17+
{
18+
"ArchStdEvent": "L1D_TLB_REFILL_WR"
19+
},
20+
{
21+
"ArchStdEvent": "L2D_CACHE_RD"
22+
},
23+
{
24+
"ArchStdEvent": "L2D_CACHE_WR"
25+
},
26+
{
27+
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
28+
},
29+
{
30+
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
31+
},
32+
{
33+
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
34+
},
35+
{
36+
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
37+
},
38+
{
39+
"ArchStdEvent": "L2D_CACHE_INVAL"
40+
},
41+
{
42+
"ArchStdEvent": "L1I_CACHE_REFILL"
43+
},
44+
{
45+
"ArchStdEvent": "L1I_TLB_REFILL"
46+
},
47+
{
48+
"ArchStdEvent": "L1D_CACHE_REFILL"
49+
},
50+
{
51+
"ArchStdEvent": "L1D_CACHE"
52+
},
53+
{
54+
"ArchStdEvent": "L1D_TLB_REFILL"
55+
},
56+
{
57+
"ArchStdEvent": "L1I_CACHE"
58+
},
59+
{
60+
"ArchStdEvent": "L2D_CACHE"
61+
},
62+
{
63+
"ArchStdEvent": "L2D_CACHE_REFILL"
64+
},
65+
{
66+
"ArchStdEvent": "L2D_CACHE_WB"
67+
},
68+
{
69+
"ArchStdEvent": "L1D_TLB"
70+
},
71+
{
72+
"ArchStdEvent": "L1I_TLB"
73+
},
74+
{
75+
"ArchStdEvent": "L2D_TLB_REFILL"
76+
},
77+
{
78+
"ArchStdEvent": "L2I_TLB_REFILL"
79+
},
80+
{
81+
"ArchStdEvent": "L2D_TLB"
82+
},
83+
{
84+
"ArchStdEvent": "L2I_TLB"
85+
},
86+
{
87+
"ArchStdEvent": "DTLB_WALK"
88+
},
89+
{
90+
"ArchStdEvent": "ITLB_WALK"
91+
},
92+
{
93+
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
94+
},
95+
{
96+
"ArchStdEvent": "L1D_CACHE_LMISS_RD"
97+
},
98+
{
99+
"ArchStdEvent": "L1I_CACHE_LMISS"
100+
},
101+
{
102+
"ArchStdEvent": "L2D_CACHE_LMISS_RD"
103+
},
104+
{
105+
"PublicDescription": "Level 1 data or unified cache demand access",
106+
"EventCode": "0x8140",
107+
"EventName": "L1D_CACHE_RW",
108+
"BriefDescription": "Level 1 data or unified cache demand access"
109+
},
110+
{
111+
"PublicDescription": "Level 1 data or unified cache preload or prefetch",
112+
"EventCode": "0x8142",
113+
"EventName": "L1D_CACHE_PRFM",
114+
"BriefDescription": "Level 1 data or unified cache preload or prefetch"
115+
},
116+
{
117+
"PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
118+
"EventCode": "0x8146",
119+
"EventName": "L1D_CACHE_REFILL_PRFM",
120+
"BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
121+
},
122+
{
123+
"ArchStdEvent": "L1D_TLB_RD"
124+
},
125+
{
126+
"ArchStdEvent": "L1D_TLB_WR"
127+
},
128+
{
129+
"ArchStdEvent": "L2D_TLB_REFILL_RD"
130+
},
131+
{
132+
"ArchStdEvent": "L2D_TLB_REFILL_WR"
133+
},
134+
{
135+
"ArchStdEvent": "L2D_TLB_RD"
136+
},
137+
{
138+
"ArchStdEvent": "L2D_TLB_WR"
139+
},
140+
{
141+
"PublicDescription": "L1D TLB miss",
142+
"EventCode": "0xD600",
143+
"EventName": "L1D_TLB_MISS",
144+
"BriefDescription": "L1D TLB miss"
145+
},
146+
{
147+
"PublicDescription": "Level 1 prefetcher, load prefetch requests generated",
148+
"EventCode": "0xd606",
149+
"EventName": "L1_PREFETCH_LD_GEN",
150+
"BriefDescription": "Level 1 prefetcher, load prefetch requests generated"
151+
},
152+
{
153+
"PublicDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache",
154+
"EventCode": "0xd607",
155+
"EventName": "L1_PREFETCH_LD_FILL",
156+
"BriefDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache"
157+
},
158+
{
159+
"PublicDescription": "Level 1 prefetcher, load prefetch to level 2 generated",
160+
"EventCode": "0xd608",
161+
"EventName": "L1_PREFETCH_L2_REQ",
162+
"BriefDescription": "Level 1 prefetcher, load prefetch to level 2 generated"
163+
},
164+
{
165+
"PublicDescription": "L1 prefetcher, distance was reset",
166+
"EventCode": "0xd609",
167+
"EventName": "L1_PREFETCH_DIST_RST",
168+
"BriefDescription": "L1 prefetcher, distance was reset"
169+
},
170+
{
171+
"PublicDescription": "L1 prefetcher, distance was increased",
172+
"EventCode": "0xd60a",
173+
"EventName": "L1_PREFETCH_DIST_INC",
174+
"BriefDescription": "L1 prefetcher, distance was increased"
175+
},
176+
{
177+
"PublicDescription": "Level 1 prefetcher, table entry is trained",
178+
"EventCode": "0xd60b",
179+
"EventName": "L1_PREFETCH_ENTRY_TRAINED",
180+
"BriefDescription": "Level 1 prefetcher, table entry is trained"
181+
},
182+
{
183+
"PublicDescription": "L1 data cache refill - Read or Write",
184+
"EventCode": "0xd60e",
185+
"EventName": "L1D_CACHE_REFILL_RW",
186+
"BriefDescription": "L1 data cache refill - Read or Write"
187+
},
188+
{
189+
"PublicDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills",
190+
"EventCode": "0xD701",
191+
"EventName": "L2C_INST_REFILL",
192+
"BriefDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills"
193+
},
194+
{
195+
"PublicDescription": "Level 2 cache refill from data-side miss, including DMMU refills",
196+
"EventCode": "0xD702",
197+
"EventName": "L2C_DATA_REFILL",
198+
"BriefDescription": "Level 2 cache refill from data-side miss, including DMMU refills"
199+
},
200+
{
201+
"PublicDescription": "Level 2 cache prefetcher, load prefetch requests generated",
202+
"EventCode": "0xD703",
203+
"EventName": "L2_PREFETCH_REQ",
204+
"BriefDescription": "Level 2 cache prefetcher, load prefetch requests generated"
205+
}
206+
]

0 commit comments

Comments
 (0)