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maurossialexdeucher
maurossi
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alexdeucher
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drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)
[Why] DCE6 has specific SCL_HORZ_FILTER_INIT_{LUMA_RGB,CHROMA} registers In DCE6 h_init_luma and h_init_chroma initialization is required Some DCE6 specific SCL_{HORZ,VERT}_FILTER_CONTROL masks were not listed [How] Add the registers and masks in dce_transform.h Add DCE6 specific struct sclh_ratios_inits in dce_transform.h Add dce60_calculate_inits() function Add dce60_program_scl_ratios_inits() function Fix dce60_transform_set_scaler() function v2: remove unused variable (Alex) Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mauro Rossi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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‎drivers/gpu/drm/amd/display/dc/dce/dce_transform.c‎

Lines changed: 67 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -306,6 +306,36 @@ static void calculate_inits(
306306
inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5;
307307
}
308308

309+
#if defined(CONFIG_DRM_AMD_DC_SI)
310+
static void dce60_calculate_inits(
311+
struct dce_transform *xfm_dce,
312+
const struct scaler_data *data,
313+
struct sclh_ratios_inits *inits)
314+
{
315+
struct fixed31_32 v_init;
316+
317+
inits->h_int_scale_ratio =
318+
dc_fixpt_u2d19(data->ratios.horz) << 5;
319+
inits->v_int_scale_ratio =
320+
dc_fixpt_u2d19(data->ratios.vert) << 5;
321+
322+
/* DCE6 h_init_luma setting inspired by DCE110 */
323+
inits->h_init_luma.integer = 1;
324+
325+
/* DCE6 h_init_chroma setting inspired by DCE110 */
326+
inits->h_init_chroma.integer = 1;
327+
328+
v_init =
329+
dc_fixpt_div_int(
330+
dc_fixpt_add(
331+
data->ratios.vert,
332+
dc_fixpt_from_int(data->taps.v_taps + 1)),
333+
2);
334+
inits->v_init.integer = dc_fixpt_floor(v_init);
335+
inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5;
336+
}
337+
#endif
338+
309339
static void program_scl_ratios_inits(
310340
struct dce_transform *xfm_dce,
311341
struct scl_ratios_inits *inits)
@@ -328,6 +358,36 @@ static void program_scl_ratios_inits(
328358
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
329359
}
330360

361+
#if defined(CONFIG_DRM_AMD_DC_SI)
362+
static void dce60_program_scl_ratios_inits(
363+
struct dce_transform *xfm_dce,
364+
struct sclh_ratios_inits *inits)
365+
{
366+
367+
REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
368+
SCL_H_SCALE_RATIO, inits->h_int_scale_ratio);
369+
370+
REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
371+
SCL_V_SCALE_RATIO, inits->v_int_scale_ratio);
372+
373+
/* DCE6 has SCL_HORZ_FILTER_INIT_RGB_LUMA register */
374+
REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0,
375+
SCL_H_INIT_INT_RGB_Y, inits->h_init_luma.integer,
376+
SCL_H_INIT_FRAC_RGB_Y, inits->h_init_luma.fraction);
377+
378+
/* DCE6 has SCL_HORZ_FILTER_INIT_CHROMA register */
379+
REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0,
380+
SCL_H_INIT_INT_CBCR, inits->h_init_chroma.integer,
381+
SCL_H_INIT_FRAC_CBCR, inits->h_init_chroma.fraction);
382+
383+
REG_SET_2(SCL_VERT_FILTER_INIT, 0,
384+
SCL_V_INIT_INT, inits->v_init.integer,
385+
SCL_V_INIT_FRAC, inits->v_init.fraction);
386+
387+
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
388+
}
389+
#endif
390+
331391
static const uint16_t *get_filter_coeffs_16p(int taps, struct fixed31_32 ratio)
332392
{
333393
if (taps == 4)
@@ -453,12 +513,14 @@ static void dce60_transform_set_scaler(
453513
is_scaling_required = dce60_setup_scaling_configuration(xfm_dce, data);
454514

455515
if (is_scaling_required) {
456-
/* 3. Calculate and program ratio, filter initialization */
457-
struct scl_ratios_inits inits = { 0 };
516+
/* 3. Calculate and program ratio, DCE6 filter initialization */
517+
struct sclh_ratios_inits inits = { 0 };
458518

459-
calculate_inits(xfm_dce, data, &inits);
519+
/* DCE6 has specific calculate_inits() function */
520+
dce60_calculate_inits(xfm_dce, data, &inits);
460521

461-
program_scl_ratios_inits(xfm_dce, &inits);
522+
/* DCE6 has specific program_scl_ratios_inits() function */
523+
dce60_program_scl_ratios_inits(xfm_dce, &inits);
462524

463525
coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert);
464526
coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz);
@@ -503,7 +565,7 @@ static void dce60_transform_set_scaler(
503565
/* 6. Program the viewport */
504566
program_viewport(xfm_dce, &data->viewport);
505567

506-
/* DCE6 does not have bit to flip to new coefficient memory */
568+
/* DCE6 has no SCL_COEF_UPDATE_COMPLETE bit to flip to new coefficient memory */
507569

508570
/* DCE6 DATA_FORMAT register does not support ALPHA_EN */
509571
}

‎drivers/gpu/drm/amd/display/dc/dce/dce_transform.h‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -331,6 +331,14 @@
331331
XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
332332
XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
333333
XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
334+
XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_INT_RGB_Y, mask_sh), \
335+
XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_FRAC_RGB_Y, mask_sh), \
336+
XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_INT_CBCR, mask_sh), \
337+
XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_FRAC_CBCR, mask_sh), \
338+
XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
339+
XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
340+
XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_FILTER_PICK_NEAREST, mask_sh), \
341+
XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_FILTER_PICK_NEAREST, mask_sh), \
334342
XFM_SF(DC_LB_MEMORY_SPLIT, DC_LB_MEMORY_CONFIG, mask_sh), \
335343
XFM_SF(DC_LB_MEM_SIZE, DC_LB_MEM_SIZE, mask_sh)
336344
#endif
@@ -497,6 +505,10 @@
497505
type SCL_V_SCALE_RATIO; \
498506
type SCL_H_INIT_INT; \
499507
type SCL_H_INIT_FRAC; \
508+
type SCL_H_INIT_INT_RGB_Y; \
509+
type SCL_H_INIT_FRAC_RGB_Y; \
510+
type SCL_H_INIT_INT_CBCR; \
511+
type SCL_H_INIT_FRAC_CBCR; \
500512
type SCL_V_INIT_INT; \
501513
type SCL_V_INIT_FRAC; \
502514
type DC_LB_MEMORY_CONFIG; \
@@ -505,6 +517,8 @@
505517
type LB_MEMORY_SIZE; \
506518
type SCL_V_2TAP_HARDCODE_COEF_EN; \
507519
type SCL_H_2TAP_HARDCODE_COEF_EN; \
520+
type SCL_V_FILTER_PICK_NEAREST; \
521+
type SCL_H_FILTER_PICK_NEAREST; \
508522
type SCL_COEF_UPDATE_COMPLETE; \
509523
type ALPHA_EN
510524

@@ -575,6 +589,10 @@ struct dce_transform_registers {
575589
uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
576590
uint32_t SCL_VERT_FILTER_SCALE_RATIO;
577591
uint32_t SCL_HORZ_FILTER_INIT;
592+
#if defined(CONFIG_DRM_AMD_DC_SI)
593+
uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA;
594+
uint32_t SCL_HORZ_FILTER_INIT_CHROMA;
595+
#endif
578596
uint32_t SCL_VERT_FILTER_INIT;
579597
uint32_t SCL_AUTOMATIC_MODE_CONTROL;
580598
#if defined(CONFIG_DRM_AMD_DC_SI)
@@ -598,6 +616,16 @@ struct scl_ratios_inits {
598616
struct init_int_and_frac v_init;
599617
};
600618

619+
#if defined(CONFIG_DRM_AMD_DC_SI)
620+
struct sclh_ratios_inits {
621+
uint32_t h_int_scale_ratio;
622+
uint32_t v_int_scale_ratio;
623+
struct init_int_and_frac h_init_luma;
624+
struct init_int_and_frac h_init_chroma;
625+
struct init_int_and_frac v_init;
626+
};
627+
#endif
628+
601629
enum ram_filter_type {
602630
FILTER_TYPE_RGB_Y_VERTICAL = 0, /* 0 - RGB/Y Vertical filter */
603631
FILTER_TYPE_CBCR_VERTICAL = 1, /* 1 - CbCr Vertical filter */

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