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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Cross-merge networking fixes after downstream PR. No conflicts. Adjacent changes: kernel/bpf/verifier.c 8299559 ("bpf: Fix verifier log for async callback return values") a923819 ("bpf: Treat first argument as return value for bpf_throw") Signed-off-by: Jakub Kicinski <[email protected]>
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‎Documentation/arch/arm64/silicon-errata.rst

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@@ -71,6 +71,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2658417 | ARM64_ERRATUM_2658417 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A520 | #2966298 | ARM64_ERRATUM_2966298 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |

‎Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml

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@@ -73,9 +73,6 @@ patternProperties:
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"^.*@[0-9a-f]+$":
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description: Devices attached to the bus
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type: object
76-
properties:
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reg:
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maxItems: 1
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required:
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- reg

‎Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

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@@ -69,7 +69,7 @@ examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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cache-controller@2010000 {
72+
cache-controller@13400000 {
7373
compatible = "andestech,ax45mp-cache", "cache";
7474
reg = <0x13400000 0x100000>;
7575
interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;

‎Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml

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@@ -87,7 +87,7 @@ required:
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- interrupts
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- ports
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additionalProperties: false
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unevaluatedProperties: false
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examples:
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- |

‎Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

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@@ -106,6 +106,12 @@ properties:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 4096
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dma-noncoherent:
110+
description:
111+
Present if the GIC redistributors permit programming shareability
112+
and cacheability attributes but are connected to a non-coherent
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downstream interconnect.
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msi-controller:
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description:
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Only present if the Message Based Interrupt functionality is
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compatible:
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const: arm,gic-v3-its
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dma-noncoherent:
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description:
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Present if the GIC ITS permits programming shareability and
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cacheability attributes but is connected to a non-coherent
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downstream interconnect.
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msi-controller: true
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"#msi-cells":

‎Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml

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@@ -37,6 +37,7 @@ properties:
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- renesas,intc-ex-r8a77990 # R-Car E3
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- renesas,intc-ex-r8a77995 # R-Car D3
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- renesas,intc-ex-r8a779a0 # R-Car V3U
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- renesas,intc-ex-r8a779f0 # R-Car S4-8
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- renesas,intc-ex-r8a779g0 # R-Car V4H
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- const: renesas,irqc
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‎Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml

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@@ -19,20 +19,19 @@ description: |
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- NMI edge select (NMI is not treated as NMI exception and supports fall edge and
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stand-up edge detection interrupts)
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
24-
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g043u-irqc # RZ/G2UL
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- renesas,r9a07g044-irqc # RZ/G2{L,LC}
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- renesas,r9a07g054-irqc # RZ/V2L
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- const: renesas,rzg2l-irqc
3230

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'#interrupt-cells':
34-
description: The first cell should contain external interrupt number (IRQ0-7) and the
35-
second cell is used to specify the flag.
32+
description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
33+
include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
34+
cell is used to specify the flag.
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const: 2
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'#address-cells':
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maxItems: 1
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interrupts:
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maxItems: 41
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minItems: 41
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items:
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- description: NMI interrupt
49+
- description: IRQ0 interrupt
50+
- description: IRQ1 interrupt
51+
- description: IRQ2 interrupt
52+
- description: IRQ3 interrupt
53+
- description: IRQ4 interrupt
54+
- description: IRQ5 interrupt
55+
- description: IRQ6 interrupt
56+
- description: IRQ7 interrupt
57+
- description: GPIO interrupt, TINT0
58+
- description: GPIO interrupt, TINT1
59+
- description: GPIO interrupt, TINT2
60+
- description: GPIO interrupt, TINT3
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- description: GPIO interrupt, TINT4
62+
- description: GPIO interrupt, TINT5
63+
- description: GPIO interrupt, TINT6
64+
- description: GPIO interrupt, TINT7
65+
- description: GPIO interrupt, TINT8
66+
- description: GPIO interrupt, TINT9
67+
- description: GPIO interrupt, TINT10
68+
- description: GPIO interrupt, TINT11
69+
- description: GPIO interrupt, TINT12
70+
- description: GPIO interrupt, TINT13
71+
- description: GPIO interrupt, TINT14
72+
- description: GPIO interrupt, TINT15
73+
- description: GPIO interrupt, TINT16
74+
- description: GPIO interrupt, TINT17
75+
- description: GPIO interrupt, TINT18
76+
- description: GPIO interrupt, TINT19
77+
- description: GPIO interrupt, TINT20
78+
- description: GPIO interrupt, TINT21
79+
- description: GPIO interrupt, TINT22
80+
- description: GPIO interrupt, TINT23
81+
- description: GPIO interrupt, TINT24
82+
- description: GPIO interrupt, TINT25
83+
- description: GPIO interrupt, TINT26
84+
- description: GPIO interrupt, TINT27
85+
- description: GPIO interrupt, TINT28
86+
- description: GPIO interrupt, TINT29
87+
- description: GPIO interrupt, TINT30
88+
- description: GPIO interrupt, TINT31
89+
- description: Bus error interrupt
90+
91+
interrupt-names:
92+
minItems: 41
93+
items:
94+
- const: nmi
95+
- const: irq0
96+
- const: irq1
97+
- const: irq2
98+
- const: irq3
99+
- const: irq4
100+
- const: irq5
101+
- const: irq6
102+
- const: irq7
103+
- const: tint0
104+
- const: tint1
105+
- const: tint2
106+
- const: tint3
107+
- const: tint4
108+
- const: tint5
109+
- const: tint6
110+
- const: tint7
111+
- const: tint8
112+
- const: tint9
113+
- const: tint10
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- const: tint11
115+
- const: tint12
116+
- const: tint13
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- const: tint14
118+
- const: tint15
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- const: tint16
120+
- const: tint17
121+
- const: tint18
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- const: tint19
123+
- const: tint20
124+
- const: tint21
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- const: tint22
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- const: tint23
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- const: tint24
128+
- const: tint25
129+
- const: tint26
130+
- const: tint27
131+
- const: tint28
132+
- const: tint29
133+
- const: tint30
134+
- const: tint31
135+
- const: bus-err
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49137
clocks:
50138
maxItems: 2
@@ -72,6 +160,23 @@ required:
72160
- power-domains
73161
- resets
74162

163+
allOf:
164+
- $ref: /schemas/interrupt-controller.yaml#
165+
166+
- if:
167+
properties:
168+
compatible:
169+
contains:
170+
const: renesas,r9a07g043u-irqc
171+
then:
172+
properties:
173+
interrupts:
174+
minItems: 42
175+
interrupt-names:
176+
minItems: 42
177+
required:
178+
- interrupt-names
179+
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unevaluatedProperties: false
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77182
examples:
@@ -80,55 +185,66 @@ examples:
80185
#include <dt-bindings/clock/r9a07g044-cpg.h>
81186
82187
irqc: interrupt-controller@110a0000 {
83-
compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
84-
reg = <0x110a0000 0x10000>;
85-
#interrupt-cells = <2>;
86-
#address-cells = <0>;
87-
interrupt-controller;
88-
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
89-
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
90-
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91-
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
92-
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
93-
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
94-
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
95-
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
96-
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
97-
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
98-
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
99-
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
100-
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
101-
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
102-
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
103-
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
104-
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
105-
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
106-
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
107-
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
108-
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
109-
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
110-
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
111-
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
112-
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
113-
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
114-
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
115-
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
116-
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
117-
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
118-
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
119-
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
120-
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
121-
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
122-
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
123-
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
124-
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
125-
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
126-
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
127-
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
128-
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
129-
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
130-
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
131-
clock-names = "clk", "pclk";
132-
power-domains = <&cpg>;
133-
resets = <&cpg R9A07G044_IA55_RESETN>;
188+
compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
189+
reg = <0x110a0000 0x10000>;
190+
#interrupt-cells = <2>;
191+
#address-cells = <0>;
192+
interrupt-controller;
193+
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
194+
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
195+
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
196+
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
197+
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
198+
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
199+
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
200+
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
201+
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
202+
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
203+
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
204+
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
205+
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
206+
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
207+
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
208+
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
209+
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
210+
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
211+
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
212+
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
213+
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
214+
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
215+
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
216+
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
217+
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
218+
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
219+
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
220+
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
221+
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
222+
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
223+
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
224+
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
225+
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
226+
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
227+
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
228+
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
229+
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
230+
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
231+
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
232+
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
233+
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
234+
interrupt-names = "nmi",
235+
"irq0", "irq1", "irq2", "irq3",
236+
"irq4", "irq5", "irq6", "irq7",
237+
"tint0", "tint1", "tint2", "tint3",
238+
"tint4", "tint5", "tint6", "tint7",
239+
"tint8", "tint9", "tint10", "tint11",
240+
"tint12", "tint13", "tint14", "tint15",
241+
"tint16", "tint17", "tint18", "tint19",
242+
"tint20", "tint21", "tint22", "tint23",
243+
"tint24", "tint25", "tint26", "tint27",
244+
"tint28", "tint29", "tint30", "tint31";
245+
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
246+
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
247+
clock-names = "clk", "pclk";
248+
power-domains = <&cpg>;
249+
resets = <&cpg R9A07G044_IA55_RESETN>;
134250
};

‎Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml

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5555
port:
5656
$ref: /schemas/graph.yaml#/$defs/port-base
57+
unevaluatedProperties: false
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5859
properties:
5960
endpoint:

‎Documentation/devicetree/bindings/media/i2c/toshiba,tc358746.yaml

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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
72+
unevaluatedProperties: false
7273
description: Input port
7374

7475
properties:
@@ -89,6 +90,7 @@ properties:
8990

9091
port@1:
9192
$ref: /schemas/graph.yaml#/$defs/port-base
93+
unevaluatedProperties: false
9294
description: Output port
9395

9496
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‎Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml

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@@ -59,7 +59,6 @@ allOf:
5959
compatible:
6060
contains:
6161
enum:
62-
- fsl,imx8mq-csi
6362
- fsl,imx8mm-csi
6463
then:
6564
required:

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