From e9703a7b0165b3e870f0c86bcce1fbb4653cda5a Mon Sep 17 00:00:00 2001 From: Chris Kjellqvist Date: Mon, 7 Nov 2022 11:40:06 -0500 Subject: [PATCH] Add all potentially necessary sources for elaborating sh_ddr module when DDR_A/B/C are present. --- .../build/scripts/synth_cl_hello_world.tcl | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl b/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl index 8d1d5c043..d9d8edebe 100644 --- a/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl +++ b/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl @@ -78,9 +78,20 @@ read_ip [ list \ # Additional IP's that might be needed if using the DDR #read_bd [ list \ -# $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci \ -# $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd +# $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd #] +#read_verilog -sv [ list \ +# $HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \ +# $HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \ +# $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_acc_axl.sv \ +# $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_gen_axl.sv \ +#] +#read_ip [ list \ +# $HDK_SHELL_DESIGN_DIR/ip/axi_clock_converter_0/axi_clock_converter_0.xci \ +# $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci +#] + + puts "AWS FPGA: Reading AWS constraints";