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3rd party simulators on vpc (#499)
* adding batch submit scripts for running 3rdparty simulations in jenkins * adding parameter to run jenkins on non-devami machine. * fixing syntax * updating modules needed for test * updating python module to get over AWSFPgaTestBase incompatibility with python3. * updating batch command to qsub * fix batch to qsub command translation * adding simulator specific options * updating cl_sde files * updating task label for internal simulations * keep f1 label until new resource created. * merging batch & regular scripts * adding Simulator fixture support in pytest * setting ADD_SIMULATOR Fixture to False in Base class * removing duplicate shell & python scripts * fixing spacing issues * updating module map for xilinx versions * fixing spacing. * updating vpc 2018.2 xilinx module name.
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‎Jenkinsfile‎

Lines changed: 60 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -22,8 +22,8 @@ properties([parameters([
2222
booleanParam(name: 'debug_fdf_uram', defaultValue: false, description: 'Debug the FDF for cl_uram_example.'),
2323
booleanParam(name: 'fdf_ddr_comb', defaultValue: false, description: 'run FDF for cl_dram_dma ddr combinations.'),
2424
booleanParam(name: 'disable_runtime_tests', defaultValue: false, description: 'Option to disable runtime tests.'),
25-
booleanParam(name: 'use_test_ami', defaultValue: false, description: 'This option asks for the test AMI from Jenkins')
26-
25+
booleanParam(name: 'use_test_ami', defaultValue: false, description: 'This option asks for the test AMI from Jenkins'),
26+
booleanParam(name: 'internal_simulations', defaultValue: false, description: 'This option asks for default agent from Jenkins')
2727
])])
2828

2929
//=============================================================================
@@ -133,6 +133,19 @@ def sdaccel_example_default_map = [ '2017.4' : [ 'Hello_World_1ddr': 'SDAccel/ex
133133
]
134134
]
135135

136+
def simulator_tool_default_map = [ '2017.4' : [ 'vivado': 'xilinx/SDx/2017.4_04112018',
137+
'vcs': 'vcs-mx/L-2016.06-1',
138+
'questa': 'questa/10.6b',
139+
'ies': 'incisive/15.20.063'
140+
],
141+
'2018.2' : [ 'vivado': 'xilinx/SDx/2018.2_06142018',
142+
'vcs': 'vcs-mx/N-2017.12-SP1-1',
143+
'questa': 'questa/10.6c_1',
144+
'ies': 'incisive/15.20.063'
145+
]
146+
]
147+
148+
136149
// Get serializable entry set
137150
@NonCPS def entrySet(m) {m.collect {k, v -> [key: k, value: v]}}
138151

@@ -150,6 +163,10 @@ def get_task_label(Map args=[ : ]) {
150163
echo "Test AMI Requested"
151164
task_label = task_label + '_test'
152165
}
166+
if (params.internal_simulations) {
167+
echo "internal simulation agent requested"
168+
task_label = 'f1'
169+
}
153170

154171
echo "Label Requested: $task_label"
155172
return task_label
@@ -341,27 +358,56 @@ if (test_fpga_tools) {
341358
}
342359
}
343360

361+
344362
if (test_sims) {
345363
all_tests['Run Sims'] = {
346364
stage('Run Sims') {
347365
def cl_names = ['cl_uram_example', 'cl_dram_dma', 'cl_hello_world']
366+
def simulators = ['vivado']
348367
def sim_nodes = [:]
368+
if(params.internal_simulations) {
369+
simulators = ['vcs', 'ies', 'questa', 'vivado']
370+
}
349371
for (x in cl_names) {
350372
for (y in xilinx_versions) {
351-
String xilinx_version = y
352-
String cl_name = x
353-
String node_name = "Sim ${cl_name} ${xilinx_version}"
354-
String key = "test_${cl_name}__"
355-
String report_file = "test_sims_${cl_name}_${xilinx_version}.xml"
356-
sim_nodes[node_name] = {
373+
for ( z in simulators) {
374+
String xilinx_version = y
375+
String cl_name = x
376+
String simulator = z
377+
String node_name = "Sim ${cl_name} ${xilinx_version}"
378+
String key = "test_${cl_name}__"
379+
String report_file = "test_sims_${cl_name}_${xilinx_version}.xml"
380+
def tool_module_map = simulator_tool_default_map.get(xilinx_version)
381+
String vcs_module = tool_module_map.get('vcs')
382+
String questa_module = tool_module_map.get('questa')
383+
String ies_module = tool_module_map.get('ies')
384+
String vivado_module = tool_module_map.get('vivado')
385+
if(params.internal_simulations) {
386+
report_file = "test_sims_${cl_name}_${xilinx_version}_${simulator}.xml"
387+
}
388+
sim_nodes[node_name] = {
357389
node(get_task_label(task: 'simulation', xilinx_version: xilinx_version)) {
358390
checkout scm
359391
try {
360-
sh """
361-
set -e
362-
source $WORKSPACE/shared/tests/bin/setup_test_hdk_env.sh
363-
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file}
364-
"""
392+
if(params.internal_simulations) {
393+
sh """
394+
set -e
395+
module purge
396+
module load python/2.7.9
397+
module load ${vivado_module}
398+
module load ${vcs_module}
399+
module load ${questa_module}
400+
module load ${ies_module}
401+
source $WORKSPACE/hdk_setup.sh
402+
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --Simulator ${simulator}
403+
"""
404+
} else {
405+
sh """
406+
set -e
407+
source $WORKSPACE/shared/tests/bin/setup_test_hdk_env.sh
408+
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --Simulator ${simulator}
409+
"""
410+
}
365411
} catch (exc) {
366412
echo "${node_name} failed: archiving results"
367413
archiveArtifacts artifacts: "hdk/cl/examples/${cl_name}/verif/sim/**", fingerprint: true
@@ -377,6 +423,7 @@ if (test_sims) {
377423
}
378424
}
379425
}
426+
}
380427
}
381428
parallel sim_nodes
382429
}

‎conftest.py‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,8 @@
2222
import pytest
2323

2424
def pytest_addoption(parser):
25+
parser.addoption("--Simulator", action="store", required=False, type=str,
26+
help="Simulator tool requested for this test", default="vivado")
2527
parser.addoption("--examplePath", action="store", required=False, type=str,
2628
help="Path to the Xilinx Example to test", default="SDAccel/examples/xilinx/getting_started/host/helloworld_ocl")
2729
parser.addoption("--rteName", action="store", required=False, type=str,
@@ -30,6 +32,11 @@ def pytest_addoption(parser):
3032
help="Xilinx Version. For eg: 2017.1, 2017.4, etc", default="2017.4")
3133

3234
def pytest_generate_tests(metafunc):
35+
36+
if metafunc.cls.ADD_SIMULATOR:
37+
print("Configuring parameters of {}::{}".format(metafunc.module.__name__, metafunc.function.__name__))
38+
print("Simulator = " + metafunc.config.getoption('Simulator'))
39+
metafunc.parametrize("Simulator", [metafunc.config.getoption('Simulator')])
3340

3441
if metafunc.cls.ADD_EXAMPLEPATH:
3542
print("Configuring parameters of {}::{}".format(metafunc.module.__name__, metafunc.function.__name__))

‎hdk/cl/examples/cl_sde/verif/scripts/Makefile‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,13 @@
1212
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
1313
# implied. See the License for the specific language governing permissions and
1414
# limitations under the License.
15-
#
16-
##
15+
16+
ifndef VIVADO_TOOL_VERSION
17+
$(error Environment variable VIVADO_TOOL_VERSION not set. please source hdk_setup.sh)
18+
else
19+
$(info VIVADO_TOOL_VERSION = $(VIVADO_TOOL_VERSION))
20+
endif
21+
1722
export TEST ?= test_null
1823
export C_TEST ?= test_null
1924

@@ -36,30 +41,27 @@ endif
3641

3742
export SIM_ROOT = $(CL_ROOT)/verif/sim/$(SIMULATOR)
3843

39-
4044
ifeq ($(C_TEST),test_null)
4145
export SIM_DIR = $(SIM_ROOT)/$(TEST)
4246
else
4347
export SIM_DIR = $(SIM_ROOT)/$(C_TEST)
4448
endif
45-
46-
49+
50+
4751
export SCRIPTS_DIR = $(PWD)
4852
export XILINX_IP = $(HDK_SHELL_DESIGN_DIR)/ip
4953
export SH_LIB_DIR = $(HDK_SHELL_DESIGN_DIR)/lib
5054
export SH_INF_DIR = $(HDK_SHELL_DESIGN_DIR)/interfaces
5155
export SH_SH_DIR = $(HDK_SHELL_DESIGN_DIR)/sh_ddr/sim
5256

53-
SV_TEST_LIST = test_hello_world
57+
SV_TEST_LIST = test_null.sv
5458
C_FILES = $(C_TEST_NAME) $(C_SDK_USR_UTILS_DIR)/sh_dpi_tasks.c $(C_COMMON_DIR)/src/fpga_pci_sv.c
5559

56-
C_TEST_LIST = test_hello_world.c
57-
5860
ifeq ($(XCHK), 1)
5961
all: make_sim_dir compile_chk run
6062
else
6163
all: make_sim_dir compile run
6264
endif
6365

64-
include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc
66+
include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc
6567

‎hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa‎

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,12 +24,24 @@
2424

2525
compile: $(COMPLIB_DIR)
2626
mkdir -p $(SIM_DIR)
27-
cd ${SIM_DIR} && ln -s -f ../questa_complib/modelsim.ini
28-
cd $(SIM_DIR) && vlog $(C_TEST_NAME) -ccflags "-I$(C_INC_DIR)"
27+
cd ${SIM_DIR} && ln -s -f ../questa_complib/modelsim.ini
28+
cd $(SIM_DIR) && vlog $(C_FILES) -ccflags "-I$(C_SDK_USR_INC_DIR)" -ccflags "-I$(C_SDK_USR_UTILS_DIR)" -ccflags "-I$(C_COMMON_DIR)/include" -ccflags "-I$(C_COMMON_DIR)/src" -ccflags "-DSV_TEST" -ccflags "-DSCOPE" -ccflags "-DQUESTA_SIM" -ccflags "-DINT_MAIN" -ccflags "-I$(C_INC_DIR)"
2929
cd $(SIM_DIR) && vlog -mfcu -sv -64 -timescale 1ps/1ps -93 -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/secureip -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f
3030

3131
run:
32-
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_12 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_13 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_11 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_11 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -do "run -all; quit -f" tb glbl $(TEST)
32+
ifeq ($(VIVADO_TOOL_VERSION), v2017.4)
33+
ifeq ($(TEST),test_null)
34+
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_15 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_16 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_14 -L $(COMPLIB_DIR)/fifo_generator_v13_2_1 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_14 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST)
35+
else
36+
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_15 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_16 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_14 -L $(COMPLIB_DIR)/fifo_generator_v13_2_1 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_14 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST)
37+
endif
38+
else
39+
ifeq ($(TEST),test_null)
40+
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST)
41+
else
42+
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST)
43+
endif
44+
endif
3345

3446
$(COMPLIB_DIR):
3547
cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl

‎hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs‎

Lines changed: 7 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -22,65 +22,16 @@
2222
## 2. make all VCS=1 -> Runs the test
2323
##################################################################
2424

25-
LOG_EXISTS=$(shell [ -e $(SIM_DIR)/$(LOG_NAME) ] && echo 1 || echo 0 )
26-
PASS_EXISTS=$(shell grep 'TEST PASSED' $(SIM_DIR)/$(LOG_NAME) | wc -l)
27-
2825
compile: $(COMPLIB_DIR)
2926
mkdir -p $(SIM_DIR)
30-
cd $(SIM_DIR) && ln -s -f $(VCS_COMPLIB_DIR)/synopsys_sim.setup
31-
ifeq ($(MAKE_DEBUG), 1)
32-
cd $(SIM_DIR) && echo "vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFAULT_DEFINES) $(DEFINES) +lint=TFIPC-L" > compile.vlogan.log
33-
cd $(SIM_DIR) && echo "vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS \"-I$(C_INC_DIR)\" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log" > compile.vcs.log
34-
else
35-
cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFAULT_DEFINES) $(DEFINES) +lint=TFIPC-L
36-
cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
37-
endif
27+
cd $(SIM_DIR) && ln -s -f ../vcs_complib/synopsys_sim.setup
28+
cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L
29+
cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
3830

3931
run:
40-
ifeq ($(MAKE_DEBUG), 1)
41-
cd $(SIM_DIR) && echo "./simv -l $(LOG_NAME) $(PLUSARGS) $(REGRESS_PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd" > $(LOG_NAME)
42-
else
43-
cd $(SIM_DIR) && ./simv -l $(LOG_NAME) $(PLUSARGS) $(REGRESS_PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd
44-
endif
45-
46-
check:
47-
ifeq ($(REGRESS), 1)
48-
@if [ $(LOG_EXISTS) -eq "1" ]; then \
49-
if [ $(PASS_EXISTS) -eq "1" ]; then \
50-
echo "$(LOG_NAME) -- PASSED" >> $(RESULTS_FILE); \
51-
else \
52-
echo "$(LOG_NAME) -- FAILED -- Did not find 'TEST PASSED' message in log file" >> $(RESULTS_FILE); \
53-
fi \
54-
else \
55-
echo "$(LOG_NAME) -- FAILED -- Did not find $(LOG_NAME) file" >> $(RESULTS_FILE); \
56-
fi
57-
endif
32+
cd $(SIM_DIR) && ./simv -l -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd
5833

59-
run_check: run check
60-
6134
$(COMPLIB_DIR):
62-
cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl
63-
cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl
64-
cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl
65-
66-
regress_clean:
67-
ifeq ($(REGRESS), 1)
68-
@rm -rf $(SIM_ROOT)
69-
@rm -rf $(RESULTS_FILE)
70-
@touch $(RESULTS_FILE)
71-
endif
72-
73-
regress_sort:
74-
@sort -o $(RESULTS_FILE) $(RESULTS_FILE)
75-
76-
regress_post_clean:
77-
@rm -rf $(SIM_DIR)/*/AN.DB
78-
@rm -rf $(SIM_DIR)/*/csrc
79-
@rm -rf $(SIM_DIR)/*/simv
80-
@rm -rf $(SIM_DIR)/*/simv.daidir
81-
@rm -rf $(SIM_DIR)/*/synopsys_sim.setup
82-
@rm -rf $(SIM_DIR)/*/tr_db.log
83-
@rm -rf $(SIM_DIR)/*/ucli.key
84-
@rm -rf $(SIM_DIR)/*/vc_hdrs.h
85-
@rm -rf $(SIM_DIR)/*/.vlogansetup.args
86-
@rm -rf $(SIM_DIR)/*/.vpd
35+
cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl
36+
cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
37+
cd $(SIM_ROOT) && rm -rf create_libs.tcl

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