Merge pull request #68 from aws/sundeep_cl_dram_dma

removed usage of aurora/hmc unused tieoff files and copied cl_axi_int…

Author: kristopk

hdk/cl/examples/cl_dram_dma/build/scripts/encrypt.tcl

@@ -50,8 +50,6 @@ file copy -force $CL_DIR/design/cl_dma_pcis_slv.sv                 $TARGET_DIR
 file copy -force $CL_DIR/design/cl_ila.sv                          $TARGET_DIR
 file copy -force $CL_DIR/design/cl_ocl_slv.sv                      $TARGET_DIR 
 file copy -force $CL_DIR/design/cl_sda_slv.sv                      $TARGET_DIR
-file copy -force $UNUSED_TEMPLATES_DIR/unused_aurora_template.inc  $TARGET_DIR
-file copy -force $UNUSED_TEMPLATES_DIR/unused_hmc_template.inc     $TARGET_DIR
 file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR
 
 #---- End of section replaced by Developr ---

hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv

@@ -30,8 +30,6 @@ module cl_dram_dma #(parameter NUM_DDR=4)
 // developers to remve the specific interfaces
 // that the CL will use
 
-`include "unused_hmc_template.inc"
-`include "unused_aurora_template.inc"
 `include "unused_sh_bar1_template.inc"
 
 // Defining local parameters that will instantiate the

hdk/common/shell_v062517b4/design/ip/cl_axi_interconnect/cl_axi_interconnect.bd

@@ -2,9 +2,9 @@
 <Root MajorVersion="0" MinorVersion="33">
   <CompositeFile CompositeFileTopName="cl_axi_interconnect" CanBeSetAsTop="true" CanDisplayChildGraph="true">
     <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1491860212"/>
-    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1491860212"/>
-    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1491860212"/>
+    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1497990864"/>
+    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1497990864"/>
+    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1497990864"/>
     <FileCollection Name="SOURCES" Type="SOURCES">
       <File Name="ip/cl_axi_interconnect_axi_interconnect_0_0/cl_axi_interconnect_axi_interconnect_0_0.xci" Type="IP">
         <Instance HierarchyPath="axi_interconnect_0"/>
@@ -54,6 +54,14 @@
         <UsedIn Val="IMPLEMENTATION"/>
         <UsedIn Val="SIMULATION"/>
       </File>
+      <File Name="ip/cl_axi_interconnect_s01_regslice_0/cl_axi_interconnect_s01_regslice_0.xci" Type="IP">
+        <Instance HierarchyPath="axi_interconnect_0/s01_couplers/s01_regslice"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
       <File Name="ip/cl_axi_interconnect_s00_regslice_0/cl_axi_interconnect_s00_regslice_0.xci" Type="IP">
         <Instance HierarchyPath="axi_interconnect_0/s00_couplers/s00_regslice"/>
         <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>