Synchrnous load and clear operations with auto-rescan and end-state display (#27)

Synchronous load and clear operations with auto-rescan and end-state display

Author: AWSrobertmj

sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt.c

@@ -23,9 +23,13 @@
 
 #include "fpga_mgmt_internal.h"
 
+/** Synchronous API (load/clear) default timeout and delay msecs */
+#define FPGA_MGMT_SYNC_TIMEOUT		300	
+#define FPGA_MGMT_SYNC_DELAY_MSEC	200 
+
 struct fgpa_mgmt_state_s fpga_mgmt_state = {
 	.timeout = FPGA_MGMT_TIMEOUT_DFLT,
-	.delay_msec = FPGA_MGMT_DELAY_MSEC_DFLT
+	.delay_msec = FPGA_MGMT_DELAY_MSEC_DFLT,
 };
 
 int fpga_mgmt_init(void)
@@ -132,14 +136,16 @@ const char *fpga_mgmt_get_status_name(int status)
 	return FPGA_STATUS2STR(status);
 }
 
-const char *fpga_mgmt_strerror(int err) {
+const char *fpga_mgmt_strerror(int err) 
+{
 	if (err < 0) {
 		return strerror(-err);
 	}
 	return FPGA_ERR2STR(err);
 }
 
-int fpga_mgmt_clear_local_image(int slot_id) {
+int fpga_mgmt_clear_local_image(int slot_id) 
+{
 	int ret;
 	uint32_t len;
 	union afi_cmd cmd;
@@ -162,7 +168,53 @@ int fpga_mgmt_clear_local_image(int slot_id) {
 	return ret;
 }
 
-int fpga_mgmt_load_local_image(int slot_id, char *afi_id) {
+int fpga_mgmt_clear_local_image_sync(int slot_id, 
+		uint32_t timeout, uint32_t delay_msec,
+		struct fpga_mgmt_image_info *info) 
+{
+	struct fpga_mgmt_image_info tmp_info;
+	uint32_t retries = 0;
+	bool done = false;
+	int status;
+	int ret;
+
+	uint32_t timeout_tmp = (timeout > FPGA_MGMT_SYNC_TIMEOUT) ?
+		timeout : FPGA_MGMT_SYNC_TIMEOUT;
+	uint32_t delay_msec_tmp = (delay_msec > FPGA_MGMT_SYNC_DELAY_MSEC) ?
+		delay_msec : FPGA_MGMT_SYNC_DELAY_MSEC;
+
+	memset(&tmp_info, 0, sizeof(tmp_info));
+
+	ret = fpga_mgmt_clear_local_image(slot_id);
+	fail_on(ret, out, "fpga_mgmt_clear_local_image failed");
+
+	while (!done) {
+		ret = fpga_mgmt_describe_local_image(slot_id, &tmp_info, 0); /** flags==0 */
+
+		status = (ret == 0) ? tmp_info.status : FPGA_STATUS_END;
+		if (status == FPGA_STATUS_CLEARED) {
+			done = true;
+		} else {
+			fail_on(ret = (retries >= timeout_tmp) ? -ETIMEDOUT : 0, out, 
+					"fpga_mgmt_describe_local_image timed out, status=%s(%d), retries=%u",
+					FPGA_STATUS2STR(status), status, retries);
+			retries++;
+			msleep(delay_msec_tmp);
+		}
+	}
+
+	ret = fpga_pci_rescan_slot_app_pfs(slot_id);
+	fail_on(ret, out, "fpga_pci_rescan_slot_app_pfs failed");
+
+	if (info) {
+		*info = tmp_info;
+	}
+out:
+	return ret;
+}
+
+int fpga_mgmt_load_local_image(int slot_id, char *afi_id) 
+{
 	int ret;
 	uint32_t len;
 	union afi_cmd cmd;
@@ -185,58 +237,113 @@ int fpga_mgmt_load_local_image(int slot_id, char *afi_id) {
 	return ret;
 }
 
-int fpga_mgmt_get_vLED_status(int slot_id, uint16_t *status) {
+int fpga_mgmt_load_local_image_sync(int slot_id, char *afi_id, 
+		uint32_t timeout, uint32_t delay_msec,
+		struct fpga_mgmt_image_info *info) 
+{
+	struct fpga_mgmt_image_info tmp_info;
+	uint32_t retries = 0;
+	bool done = false;
+	int status;
 	int ret;
-	pci_bar_handle_t	led_pci_bar;
-	uint32_t	read_data;
 
-	ret=fpga_pci_attach(slot_id, FPGA_MGMT_PF, MGMT_PF_BAR0, 0, &led_pci_bar);
-	if (ret) 
-		return FPGA_ERR_FAIL;
+	uint32_t timeout_tmp = (timeout > FPGA_MGMT_SYNC_TIMEOUT) ?
+		timeout : FPGA_MGMT_SYNC_TIMEOUT;
+	uint32_t delay_msec_tmp = (delay_msec > FPGA_MGMT_SYNC_DELAY_MSEC) ?
+		delay_msec : FPGA_MGMT_SYNC_DELAY_MSEC;
+
+	memset(&tmp_info, 0, sizeof(tmp_info));
+
+	ret = fpga_mgmt_load_local_image(slot_id, afi_id);
+	fail_on(ret, out, "fpga_mgmt_load_local_image failed");
+
+	while (!done) {
+		ret = fpga_mgmt_describe_local_image(slot_id, &tmp_info, 0); /** flags==0 */
+
+		status = (ret == 0) ? tmp_info.status : FPGA_STATUS_END;
+		if (status == FPGA_STATUS_LOADED) {
+			/** Sanity check the afi_id */
+			ret = strncmp(afi_id, tmp_info.ids.afi_id, sizeof(tmp_info.ids.afi_id)); 
+			fail_on(ret, out, "AFI ID mismatch: requested afi_id=%s, loaded afi_id=%s",
+					afi_id, tmp_info.ids.afi_id);
+			done = true;
+		} else {
+			fail_on(ret = (retries >= timeout_tmp) ? -ETIMEDOUT : 0, out, 
+					"fpga_mgmt_describe_local_image timed out, status=%s(%d), retries=%u",
+					FPGA_STATUS2STR(status), status, retries);
+			retries++;
+			msleep(delay_msec_tmp);
+		}
+	}
+
+	ret = fpga_pci_rescan_slot_app_pfs(slot_id);
+	fail_on(ret, out, "fpga_pci_rescan_slot_app_pfs failed");
+
+	if (info) {
+		*info = tmp_info;
+	}
+out:
+	return ret;
+}
+
+int fpga_mgmt_get_vLED_status(int slot_id, uint16_t *status) 
+{
+	pci_bar_handle_t led_pci_bar;
+	uint32_t read_data;
+	int ret;
+
+	ret = fpga_pci_attach(slot_id, FPGA_MGMT_PF, MGMT_PF_BAR0, 0, &led_pci_bar);
+	fail_on(ret, out, "fpga_pci_attach failed");
 
-	ret = fpga_pci_peek(led_pci_bar,F1_VIRTUAL_LED_REG_OFFSET,&read_data);
-       /* All this code assumes little endian, it would need rework for supporting non x86/arm platforms */
-        *(status) = (uint16_t)( read_data & 0x0000FFFF);
+	ret = fpga_pci_peek(led_pci_bar, F1_VIRTUAL_LED_REG_OFFSET, &read_data);
+	fail_on(ret, out, "fpga_pci_peek failed");
 
+	/* All this code assumes little endian, it would need rework for supporting non x86/arm platforms */
+	*status = (uint16_t)(read_data & 0x0000FFFF);
 
-	fpga_pci_detach(led_pci_bar);
+	ret = fpga_pci_detach(led_pci_bar);
+	fail_on(ret, out, "fpga_pci_detach failed");
+out:
 	return ret;	
 }
 
-int fpga_mgmt_set_vDIP(int slot_id, uint16_t value) {
-        int ret;
-        pci_bar_handle_t        dip_pci_bar;
-        uint32_t        write_data;
-
-        ret=fpga_pci_attach(slot_id, FPGA_MGMT_PF, MGMT_PF_BAR0, 0, &dip_pci_bar);
-        if (ret)
-                return FPGA_ERR_FAIL;
+int fpga_mgmt_set_vDIP(int slot_id, uint16_t value) 
+{
+	pci_bar_handle_t dip_pci_bar;
+	uint32_t write_data;
+	int ret;
 
+	ret = fpga_pci_attach(slot_id, FPGA_MGMT_PF, MGMT_PF_BAR0, 0, &dip_pci_bar);
+	fail_on(ret, out, "fpga_pci_attach failed");
 
 	write_data = (uint32_t) value;
 
-        ret = fpga_pci_poke(dip_pci_bar,F1_VIRTUAL_DIP_REG_OFFSET,write_data);
-
+	ret = fpga_pci_poke(dip_pci_bar, F1_VIRTUAL_DIP_REG_OFFSET, write_data);
+	fail_on(ret, out, "fpga_pci_poke failed");
 
-        fpga_pci_detach(dip_pci_bar);
-        return ret;
+	ret = fpga_pci_detach(dip_pci_bar);
+	fail_on(ret, out, "fpga_pci_detach failed");
+out:
+	return ret;
 }
 
-int fpga_mgmt_get_vDIP_status(int slot_id, uint16_t *value) {
-
-        int ret;
-        pci_bar_handle_t        dip_pci_bar;
-        uint32_t        read_data;
+int fpga_mgmt_get_vDIP_status(int slot_id, uint16_t *value) 
+{
+	pci_bar_handle_t dip_pci_bar;
+	uint32_t read_data;
+	int ret;
 
-        ret=fpga_pci_attach(slot_id, FPGA_MGMT_PF, MGMT_PF_BAR0, 0, &dip_pci_bar);
-        if (ret)
-                return FPGA_ERR_FAIL;
+	ret = fpga_pci_attach(slot_id, FPGA_MGMT_PF, MGMT_PF_BAR0, 0, &dip_pci_bar);
+	fail_on(ret, out, "fpga_pci_attach failed");
 
-        ret = fpga_pci_peek(dip_pci_bar,F1_VIRTUAL_DIP_REG_OFFSET,&read_data);
-       /* All this code assumes little endian, it would need rework for supporting non x86/arm platforms */
-	 *(value) = (uint16_t)read_data; 
+	ret = fpga_pci_peek(dip_pci_bar, F1_VIRTUAL_DIP_REG_OFFSET, &read_data);
+	fail_on(ret, out, "fpga_pci_peek failed");
 
-        fpga_pci_detach(dip_pci_bar);
-        return ret;
+	/* All this code assumes little endian, it would need rework for supporting non x86/arm platforms */
+	*value = (uint16_t)read_data; 
 
+	ret = fpga_pci_detach(dip_pci_bar);
+	fail_on(ret, out, "fpga_pci_detach failed");
+out:
+	return ret;
 }

sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c

@@ -385,12 +385,12 @@ fpga_mgmt_afi_validate_header(const union afi_cmd *cmd,
 	fail_on_quiet(!is_response, err, "Command is not a response");
 	return 0;
 
-id_err:
-	return -EAGAIN;
 op_err:
 	if (rsp->hdr.op == AFI_CMD_ERROR) {
 		return fpga_mgmt_handle_afi_cmd_error_rsp(rsp, len);
 	}
+id_err:
+	return -EAGAIN;
 err:
 	return FPGA_ERR_FAIL;
 }
@@ -411,18 +411,20 @@ fpga_mgmt_send_cmd(int slot_id,
 	 *  -also make a minimal attempt to drain stale responses
 	 *   (if any).
 	 */
-	uint32_t id_retries = 0;
-	ret = -EAGAIN;
-	while (ret == -EAGAIN) {
+	uint32_t retries = 0;
+	bool done = false;
+	while (!done) {
 		ret = fpga_hal_mbox_read(handle, (void *)rsp, len);
 		fail_on(ret = (ret) ? (-ETIMEDOUT) : 0, err_code, "Error: operation timed out");
 
 		ret = fpga_mgmt_afi_validate_header(cmd, rsp, *len);
-		fail_on(ret, err_code, CLI_INTERNAL_ERR_STR);
-
-		fail_on(id_retries >= AFI_MAX_ID_RETRIES, err,
-				CLI_INTERNAL_ERR_STR);
-		id_retries++;
+		if (ret == 0) {
+			done = true;
+		} else {
+			fail_on(ret != -EAGAIN, err_code, CLI_INTERNAL_ERR_STR);
+			fail_on(retries >= AFI_MAX_RETRIES, err, CLI_INTERNAL_ERR_STR);
+			retries++;
+		}
 	}
 	fail_on(ret != 0, err, CLI_INTERNAL_ERR_STR);
 

sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_internal.h

@@ -26,8 +26,8 @@
 /** Mask to get the length portion, @see afi_cmd_hdr#len_flags */
 #define AFI_CMD_HDR_LEN_MASK    ((1 << AFI_CMD_HDR_FLAGS_SHIFT) - 1)
 
-/** Max retriees for draining presumed stale AFI commands */
-#define AFI_MAX_ID_RETRIES		1
+/** Max retries for draining presumed stale AFI commands */
+#define AFI_MAX_RETRIES		1
 
 #define CLI_INTERNAL_ERR_STR "Error: Internal error "
 

sdk/userspace/fpga_libs/fpga_pci/fpga_pci_internal.h

@@ -28,7 +28,7 @@
 
 /** F1 Application PF defines */
 #define F1_MBOX_DEV2APP_DEV(dev)		((dev) - 1)
-#define F1_REMOVE_APP_PF_DELAY_MSEC		1000
-#define F1_REMOVE_APP_PF_MAX_RETRIES	3
+#define F1_CHECK_APP_PF_DELAY_MSEC		1000
+#define F1_CHECK_APP_PF_MAX_RETRIES	3
 
 #define CLI_INTERNAL_ERR_STR "Error: Internal error "