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AWSaalluriAWSaalluri
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virtual ethernet branch PR into develop (#451)
* sdk/apps/virtual-ethernet: added sdk/apps directory for virtual ethernet * Update Virtual_Ethernet_Application_Guide.md * Update Virtual_Ethernet_Application_Guide.md * sdk/apps/virtual-ethernet: pktgen updates * use dpdk-v18.0.5 and the latest compatible version of pktgen * pktgen patches for ENA * pktgen memory leak fixes * Update Virtual_Ethernet_Application_Guide.md * Update Virtual_Ethernet_Application_Guide.md * sdk/apps/virtual-ethernet: modified the VID/DIDs for the SDE loopback CL * Porting CL_SDE from chimera to github CL examples. Adding ILA ips needed under CL. Full validation not yet done. commiting for license header review. new file: cl_sde/build/constraints/cl_pnr_user.xdc new file: cl_sde/build/constraints/cl_synth_user.xdc new file: cl_sde/build/scripts/aws_build_dcp_from_cl.sh new file: cl_sde/build/scripts/create_dcp_from_cl.tcl new file: cl_sde/build/scripts/encrypt.tcl new file: cl_sde/build/scripts/synth_cl_sde.tcl new file: cl_sde/design/axi_prot_chk.sv new file: cl_sde/design/cl_id_defines.vh new file: cl_sde/design/cl_sde.sv new file: cl_sde/design/cl_sde_srm.sv new file: cl_sde/design/sde.sv new file: cl_sde/design/sde_c2h.sv new file: cl_sde/design/sde_c2h_axis.sv new file: cl_sde/design/sde_c2h_buf.sv new file: cl_sde/design/sde_c2h_cfg.sv new file: cl_sde/design/sde_c2h_data.sv new file: cl_sde/design/sde_desc.sv new file: cl_sde/design/sde_h2c.sv new file: cl_sde/design/sde_h2c_axis.sv new file: cl_sde/design/sde_h2c_buf.sv new file: cl_sde/design/sde_h2c_cfg.sv new file: cl_sde/design/sde_h2c_data.sv new file: cl_sde/design/sde_pkg.sv new file: cl_sde/design/sde_pm.sv new file: cl_sde/design/sde_ps.sv new file: cl_sde/design/sde_ps_acc.sv new file: cl_sde/design/sde_wb.sv new file: cl_sde/ip/ila_axi4/doc/ila_v6_2_changelog.txt new file: cl_sde/ip/ila_axi4/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd new file: cl_sde/ip/ila_axi4/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd new file: cl_sde/ip/ila_axi4/hdl/ila_v6_2_syn_rfs.v new file: cl_sde/ip/ila_axi4/hdl/ltlib_v1_0_vl_rfs.v new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_in.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_lparam.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_param.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_ver.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/ltlib_v1_0_0_lib_fn.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/ltlib_v1_0_0_ver.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_core.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_i2x.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_icn.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_id_map.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_in.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbs_v1_0_2_i2x.vh new file: cl_sde/ip/ila_axi4/hdl/verilog/xsdbs_v1_0_2_in.vh new file: cl_sde/ip/ila_axi4/hdl/xsdbm_v3_0_vl_rfs.v new file: cl_sde/ip/ila_axi4/hdl/xsdbs_v1_0_vl_rfs.v new file: cl_sde/ip/ila_axi4/ila_axi4.veo new file: cl_sde/ip/ila_axi4/ila_axi4.xci new file: cl_sde/ip/ila_axi4/ila_axi4.xml new file: cl_sde/ip/ila_axi4/ila_axi4_ooc.xdc new file: cl_sde/ip/ila_axi4/ila_v6_2/constraints/ila.xdc new file: cl_sde/ip/ila_axi4/ila_v6_2/constraints/ila_impl.xdc new file: cl_sde/ip/ila_axi4/sim/ila_axi4.v new file: cl_sde/ip/ila_axi4/synth/ila_axi4.v new file: cl_sde/ip/ila_axi4_512/doc/ila_v6_2_changelog.txt new file: cl_sde/ip/ila_axi4_512/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd new file: cl_sde/ip/ila_axi4_512/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd new file: cl_sde/ip/ila_axi4_512/hdl/ila_v6_2_syn_rfs.v new file: cl_sde/ip/ila_axi4_512/hdl/ltlib_v1_0_vl_rfs.v new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_in.vh new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh new file: cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_lparam.vh new file: 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cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_in.vh new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbs_v1_0_2_i2x.vh new file: cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbs_v1_0_2_in.vh new file: cl_sde/ip/ila_axi4_512/hdl/xsdbm_v3_0_vl_rfs.v new file: cl_sde/ip/ila_axi4_512/hdl/xsdbs_v1_0_vl_rfs.v new file: cl_sde/ip/ila_axi4_512/ila_axi4_512.veo new file: cl_sde/ip/ila_axi4_512/ila_axi4_512.xci new file: cl_sde/ip/ila_axi4_512/ila_axi4_512.xml new file: cl_sde/ip/ila_axi4_512/ila_axi4_512_ooc.xdc new file: cl_sde/ip/ila_axi4_512/ila_v6_2/constraints/ila.xdc new file: cl_sde/ip/ila_axi4_512/ila_v6_2/constraints/ila_impl.xdc new file: cl_sde/ip/ila_axi4_512/sim/ila_axi4_512.v new file: cl_sde/ip/ila_axi4_512/synth/ila_axi4_512.v new file: cl_sde/ip/ila_axis/doc/ila_v6_2_changelog.txt new file: cl_sde/ip/ila_axis/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd 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cl_sde/ip/ila_sde_h2c_dm/ila_v6_2/constraints/ila_impl.xdc new file: cl_sde/ip/ila_sde_h2c_dm/sim/ila_sde_h2c_dm.v new file: cl_sde/ip/ila_sde_h2c_dm/synth/ila_sde_h2c_dm.v new file: cl_sde/ip/ila_sde_ps/doc/ila_v6_2_changelog.txt new file: cl_sde/ip/ila_sde_ps/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd new file: cl_sde/ip/ila_sde_ps/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd new file: cl_sde/ip/ila_sde_ps/hdl/ila_v6_2_syn_rfs.v new file: cl_sde/ip/ila_sde_ps/hdl/ltlib_v1_0_vl_rfs.v new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_in.vh new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_lparam.vh new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_param.vh new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_ver.vh new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ltlib_v1_0_0_lib_fn.vh new file: cl_sde/ip/ila_sde_ps/hdl/verilog/ltlib_v1_0_0_ver.vh new file: cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs.vh 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cl_sde/ip/ila_sde_ps/hdl/xsdbs_v1_0_vl_rfs.v new file: cl_sde/ip/ila_sde_ps/ila_sde_ps.veo new file: cl_sde/ip/ila_sde_ps/ila_sde_ps.xci new file: cl_sde/ip/ila_sde_ps/ila_sde_ps.xml new file: cl_sde/ip/ila_sde_ps/ila_sde_ps_ooc.xdc new file: cl_sde/ip/ila_sde_ps/ila_v6_2/constraints/ila.xdc new file: cl_sde/ip/ila_sde_ps/ila_v6_2/constraints/ila_impl.xdc new file: cl_sde/ip/ila_sde_ps/sim/ila_sde_ps.v new file: cl_sde/ip/ila_sde_ps/synth/ila_sde_ps.v new file: cl_sde/ip/ila_sde_wb/doc/ila_v6_2_changelog.txt new file: cl_sde/ip/ila_sde_wb/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd new file: cl_sde/ip/ila_sde_wb/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd new file: cl_sde/ip/ila_sde_wb/hdl/ila_v6_2_syn_rfs.v new file: cl_sde/ip/ila_sde_wb/hdl/ltlib_v1_0_vl_rfs.v new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_in.vh new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh new file: cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_lparam.vh new file: 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cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_in.vh new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbs_v1_0_2_i2x.vh new file: cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbs_v1_0_2_in.vh new file: cl_sde/ip/ila_sde_wb/hdl/xsdbm_v3_0_vl_rfs.v new file: cl_sde/ip/ila_sde_wb/hdl/xsdbs_v1_0_vl_rfs.v new file: cl_sde/ip/ila_sde_wb/ila_sde_wb.veo new file: cl_sde/ip/ila_sde_wb/ila_sde_wb.xci new file: cl_sde/ip/ila_sde_wb/ila_sde_wb.xml new file: cl_sde/ip/ila_sde_wb/ila_sde_wb_ooc.xdc new file: cl_sde/ip/ila_sde_wb/ila_v6_2/constraints/ila.xdc new file: cl_sde/ip/ila_sde_wb/ila_v6_2/constraints/ila_impl.xdc new file: cl_sde/ip/ila_sde_wb/sim/ila_sde_wb.v new file: cl_sde/ip/ila_sde_wb/synth/ila_sde_wb.v new file: cl_sde/software/include/.gitignore new file: cl_sde/software/include/sh_dpi_tasks.h new file: cl_sde/software/src/.gitignore new file: cl_sde/software/src/test_null.c new file: cl_sde/verif/scripts/Makefile new file: cl_sde/verif/scripts/Makefile.questa new file: cl_sde/verif/scripts/Makefile.vcs new file: cl_sde/verif/scripts/Makefile.vivado new file: cl_sde/verif/scripts/regress_err_handle new file: cl_sde/verif/scripts/regress_nightly new file: cl_sde/verif/scripts/regress_nightly_16K new file: cl_sde/verif/scripts/regress_nightly_32K new file: cl_sde/verif/scripts/regress_nightly_4K new file: cl_sde/verif/scripts/regress_nightly_8K new file: cl_sde/verif/scripts/regress_smoke new file: cl_sde/verif/scripts/top.questa.f new file: cl_sde/verif/scripts/top.vcs.f new file: cl_sde/verif/scripts/top.vivado.f new file: cl_sde/verif/scripts/waves.tcl new file: cl_sde/verif/sv/dma_classes.sv new file: cl_sde/verif/sv/perf_mon.sv new file: cl_sde/verif/tests/test_base.inc new file: cl_sde/verif/tests/test_c2h_h2c_using_atg.sv new file: cl_sde/verif/tests/test_desc_access.sv new file: cl_sde/verif/tests/test_null.sv new file: cl_sde/verif/tests/test_pci_atg.sv new file: cl_sde/verif/tests/test_random_c2h.sv new file: cl_sde/verif/tests/test_random_combined.sv new file: cl_sde/verif/tests/test_random_h2c.sv new file: cl_sde/verif/tests/test_simple_c2h.sv new file: cl_sde/verif/tests/test_simple_c2h_desc_oflow.sv new file: cl_sde/verif/tests/test_simple_c2h_desc_ooo.sv new file: cl_sde/verif/tests/test_simple_c2h_desc_unalin.sv new file: cl_sde/verif/tests/test_simple_c2h_dm_desc_len_err.sv new file: cl_sde/verif/tests/test_simple_c2h_pcim_bresp_err.sv new file: cl_sde/verif/tests/test_simple_h2c.sv new file: cl_sde/verif/tests/test_simple_h2c_desc_oflow.sv new file: cl_sde/verif/tests/test_simple_h2c_desc_ooo.sv new file: cl_sde/verif/tests/test_simple_h2c_desc_unalin.sv new file: cl_sde/verif/tests/test_simple_h2c_dm_desc_len_err.sv new file: cl_sde/verif/tests/test_simple_h2c_pcim_bresp_err.sv new file: cl_sde/verif/tests/test_simple_h2c_pcim_rresp_err.sv * adding the lib files & other missing files. updated file paths Licensing needs to be attached: pending. * 1. updating CL_ID 2. Porting the writeback file from chimera for bug fix modified: hdk/cl/examples/cl_sde/design/cl_sde.sv modified: hdk/cl/examples/cl_sde/design/sde_wb.sv modified: hdk/cl/examples/cl_sde/lib/bram_1w1r.sv * sdk/apps/virtual-ethernet: Added pktgen-ena-range config for improved PPS consistency Also allows customer tuning of packet size ranges * Update Virtual_Ethernet_Application_Guide.md * sdk/apps/virtual-ethernet: changes to support DPDK v18.05 * sdk/apps/virtual-ethernet: DPDK v18.05 related - Added RTE_MEMZONE_IOVA_CONTIG to memzone reservation calls to get the previous default memzone reservation behavior. * Update Virtual_Ethernet_Application_Guide.md * sdk/apps/virtual-ethernet: added mbuf trailer checking for SPP_DBG_USE_MBUF_SEQ_NUM * Create README.md * Update README.md * Update README.md * porting bug updates from chimera as indicated by kiran. validated customer flow. modified: hdk/cl/examples/cl_sde/design/sde.sv modified: hdk/cl/examples/cl_sde/design/sde_c2h.sv modified: hdk/cl/examples/cl_sde/design/sde_c2h_axis.sv modified: hdk/cl/examples/cl_sde/design/sde_c2h_buf.sv modified: hdk/cl/examples/cl_sde/design/sde_c2h_cfg.sv modified: hdk/cl/examples/cl_sde/design/sde_c2h_data.sv modified: hdk/cl/examples/cl_sde/design/sde_desc.sv modified: hdk/cl/examples/cl_sde/design/sde_h2c.sv modified: hdk/cl/examples/cl_sde/design/sde_h2c_axis.sv modified: hdk/cl/examples/cl_sde/design/sde_h2c_buf.sv modified: hdk/cl/examples/cl_sde/design/sde_h2c_data.sv modified: hdk/cl/examples/cl_sde/design/sde_pkg.sv modified: hdk/cl/examples/cl_sde/design/sde_pm.sv modified: hdk/cl/examples/cl_sde/design/sde_ps.sv modified: hdk/cl/examples/cl_sde/design/sde_ps_acc.sv modified: hdk/cl/examples/cl_sde/design/sde_wb.sv * Update README.md * Update README.md * Update SDE_HW_Guide.md * Update README.md * Update README.md * Update README.md * Update README.md * updating sde example with expanded customer configurations * porting changes made directly to preview back to staging -branch some updates mainly documentation & software patches were made directly to preview area. Porting them back to staging branch. * Robertmj sde compact descs (#434) * Added SDE info support * allows dynamic queue size discovery by testpmd * allows sanity checking of unsupported SDE configs. * Added SDE compact descriptor support. * see SPP_USE_COMPACT_DESCS in spp_defs.h * Update Virtual_Ethernet_Application_Guide.md * Update Virtual_Ethernet_Application_Guide.md * updating license headers for jenkins header check * fixing license header issues * further license header cleanup * fixing license headers * script to generate IP and associated collateral * updates jenkins on v141 branch with cl_sde dcp build ,create afi & cl_sde runtime loopback placeholder. * updated softlink for script to stay within repo * updating AFI to a rebased version DevKit 1.4.1 * Updated SDE resource counts * Optimizations to SDE. * SDE: Increasing Number of OT Reads * Fixing license headers * Fixing read txn fifo * Revert "Fixing license headers" This reverts commit 4147ec74a329166fb75c0b1c197732bca1231f8a. * Revert "SDE: Increasing Number of OT Reads" This reverts commit 7613db06cee03f648df17ee3e4e640bb0f7de719. * Revert "Optimizations to SDE." This reverts commit ba9d165166ecc9a9bde17dfcdb39ba0acc4c6456. * Revert "Fixing read txn fifo" This reverts commit 858df502505bf4eeb692c02879fd5f133f814575. * updating qual run.
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‎hdk/cl/examples/cl_sde/README.md

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# CL_SDE Custom Logic Example
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## Table of Contents
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1. [Overview](#Overview)
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2. [Functional Description](#FuncDesc)
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3. [Interfaces and Address Range](#Interfaces)
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3. [Software](#Software)
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3. [Metadata](#Metadata)
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<a name="Overview"></a>
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## Overview
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The CL_SDE example implements the FPGA custom logic used to generate the AFI to demonstrate the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md). The CL_SDE demonstrates the following -
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1. Using the [Streaming Data Engine](../../../../sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md) (SDE) IP Block in your custom logic.
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2. Connectivity between the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md) and the SDE.
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3. Connectivity between the Shell and the SDE.
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3. Clocks and Resets for the SDE.
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4. Floorplanning and Implemention with the SDE including pipelining for AXI buses, resets etc.
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### System Diagram
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![alt tag](../../../../sdk/apps/virtual-ethernet/images/CL_SDE_Block_Diagram.jpg)
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<a name="FuncDesc"></a>
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## Functional Description
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The following functionality is implemented in the CL_SDE -
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1. Capability to loopback from H2C and C2H.
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2. Memory to store and read H2C packets for H2C functional testing
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3. AXI Stream Traffic Generator for C2H functional and performance testing
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4. AXI4 Traffic Generator for PCIM performance testing
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5. Configuration and Reset generation logic.
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6. Pipelining for PCIM and PCIS interfaces.
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See [SDE HW Guide](../../../../sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md) for details about the functional description of the SDE.
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<a name="Interfaces"></a>
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## Interfaces and Address Range
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### Interfaces
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CL_SDE uses two interfaces from the Shell.
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The PCIS interface is used to provide connectivity between the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md) and the SDE.
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The OCL interface is used to provide connectivity between the host and all the test/control/utility blocks (except the SDE).
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The PCIM interfaces is used by the SDE to read and write to host memory.
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### Address Range
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#### PCIS
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| Low Address | High Address | Description |
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|-------------|--------------|-------------|
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| 0x00_0000_0000 | 0x00_0000_3FFF | [SDE](../../../../sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md) |
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| 0x00_0000_4000 | 0x1F_FFFF_FFFF | Unused |
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#### OCL
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| Low Address | High Address | Description |
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|-------------|--------------|-------------|
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| 0x0000_0000 | 0x0000_017F | AXI-Stream Automatic Traffic Generator |
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| 0x0000_0180 | 0x0000_0FFF | Loopback Block |
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| 0x0000_1000 | 0x0000_10FF | Unused |
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| 0x0000_1100 | 0x0000_11FF | AXI4 Automatic Traffic Generator |
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| 0x0000_1200 | 0x0000_1FFF | Unused |
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| 0x0000_2000 | 0x0000_2FFF | CL Reset and Control |
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| 0x0000_3000 | 0x0200_0000 | Unused |
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<a name="Software"></a>
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## Software
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The software is provided as part of the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md).
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<a name="Metadata"></a>
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## CL_SDE Example Metadata
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The following table displays information about the CL that is required to register it as an AFI with AWS. Alternatively, you can directly use a pre-generated AFI for this CL.
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| Key | Value |
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|-----------|------|
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| Shell Version | 0x04261818 |
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| PCI Device ID | 0xF002 |
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| PCI Vendor ID | 0x1D0F (Amazon) |
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| PCI Subsystem ID | 0x1D51 |
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| PCI Subsystem Vendor ID | 0xFEDC |
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| Pre-generated AFI ID (N.Virginia:us-east-1) | afi-08fca33060fff4a62 |
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| Pre-generated AGFI ID | agfi-0f4eca32dc6100729 |

‎hdk/cl/examples/cl_sde/build/constraints/cl_pnr_user.xdc

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# This contains the CL specific constraints for Top level PNR
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set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
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set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
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set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
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create_pblock pblock_CL_top
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resize_pblock [get_pblocks pblock_CL_top] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14}
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set_property PARENT pblock_CL [get_pblocks pblock_CL_top]
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create_pblock pblock_CL_mid
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add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/AXIL_OCL_REG_SLC_MID_SLR/*}]
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add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/PCIM_REG_SLC_MID_SLR/*}]
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add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/PCIS_REG_SLC_MID_SLR/*}]
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add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SDE/*}]
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add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/CL_SDE_SRM/*}]
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add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/CL_TST_PCIM/*}]
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#not yet# add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/PIPE_RST_N_MID_SLR/*}]
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#1.3 Shell#
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#resize_pblock [get_pblocks pblock_CL_mid] -add {CLOCKREGION_X0Y5:CLOCKREGION_X3Y9}
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#1.4 Shell#
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resize_pblock [get_pblocks pblock_CL_mid] -add {SLICE_X88Y300:SLICE_X107Y599}
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resize_pblock [get_pblocks pblock_CL_mid] -add {DSP48E2_X11Y120:DSP48E2_X13Y239}
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resize_pblock [get_pblocks pblock_CL_mid] -add {LAGUNA_X12Y240:LAGUNA_X15Y479}
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resize_pblock [get_pblocks pblock_CL_mid] -add {RAMB18_X7Y120:RAMB18_X7Y239}
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resize_pblock [get_pblocks pblock_CL_mid] -add {RAMB36_X7Y60:RAMB36_X7Y119}
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resize_pblock [get_pblocks pblock_CL_mid] -add {URAM288_X2Y80:URAM288_X2Y159}
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resize_pblock [get_pblocks pblock_CL_mid] -add {CLOCKREGION_X0Y5:CLOCKREGION_X2Y9}
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set_property SNAPPING_MODE ON [get_pblocks pblock_CL_mid]
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set_property PARENT pblock_CL [get_pblocks pblock_CL_mid]
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create_pblock pblock_CL_bot
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add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/AXIL_OCL_REG_SLC_BOT_SLR/*}]
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add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/PCIS_REG_SLC_BOT_SLR/*}]
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#not yet# add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/PIPE_RST_N_BOT_SLR/*}]
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#1.3 Shell#
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#resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y4}
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#1.4 Shell#
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resize_pblock [get_pblocks pblock_CL_bot] -add {SLICE_X88Y0:SLICE_X107Y299}
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resize_pblock [get_pblocks pblock_CL_bot] -add {DSP48E2_X11Y0:DSP48E2_X13Y119}
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resize_pblock [get_pblocks pblock_CL_bot] -add {LAGUNA_X12Y0:LAGUNA_X15Y239}
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resize_pblock [get_pblocks pblock_CL_bot] -add {RAMB18_X7Y0:RAMB18_X7Y119}
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resize_pblock [get_pblocks pblock_CL_bot] -add {RAMB36_X7Y0:RAMB36_X7Y59}
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resize_pblock [get_pblocks pblock_CL_bot] -add {URAM288_X2Y0:URAM288_X2Y79}
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resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X2Y4}
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set_property SNAPPING_MODE ON [get_pblocks pblock_CL_bot]
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set_property PARENT pblock_CL [get_pblocks pblock_CL_bot]
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# Remove physical connstraints for ILAs
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remove_cells_from_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SDE/*ILA}]
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add_cells_to_pblock [get_pblocks pblock_CL] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SDE/*ILA}]
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‎hdk/cl/examples/cl_sde/build/constraints/cl_synth_user.xdc

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## # This contains the CL specific constraints for synthesis at the CL level
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## set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]]
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## set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]]
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‎hdk/cl/examples/cl_sde/build/scripts/aws_build_dcp_from_cl.sh

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../../../../../common/shell_stable/build/scripts/aws_build_dcp_from_cl.sh

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