@@ -25,11 +25,11 @@ struct i2s_descr_t {
2525 I2S_HandleTypeDef i2s;
2626 DMA_HandleTypeDef dmatx;
2727 IRQn_Type dmatx_irqn;
28- DMABufferPool <Sample> *dmatx_pool;
28+ DMAPool <Sample> *dmatx_pool;
2929 DMABuffer<Sample> *dmatx_buf[2 ];
3030 DMA_HandleTypeDef dmarx;
3131 IRQn_Type dmarx_irqn;
32- DMABufferPool <Sample> *dmarx_pool;
32+ DMAPool <Sample> *dmarx_pool;
3333 DMABuffer<Sample> *dmarx_buf[2 ];
3434};
3535
@@ -154,16 +154,16 @@ static int i2s_start_dma_transfer(i2s_descr_t *descr, i2s_mode_t i2s_mode) {
154154
155155 if (i2s_mode & AN_I2S_MODE_IN) {
156156 // Start I2S DMA.
157- descr->dmarx_buf [0 ] = descr->dmarx_pool ->allocate ( );
158- descr->dmarx_buf [1 ] = descr->dmarx_pool ->allocate ( );
157+ descr->dmarx_buf [0 ] = descr->dmarx_pool ->alloc (DMA_BUFFER_WRITE );
158+ descr->dmarx_buf [1 ] = descr->dmarx_pool ->alloc (DMA_BUFFER_WRITE );
159159 rx_buf = (uint16_t *) descr->dmarx_buf [0 ]->data ();
160160 buf_size = descr->dmarx_buf [0 ]->size ();
161161 HAL_NVIC_DisableIRQ (descr->dmarx_irqn );
162162 }
163163
164164 if (i2s_mode & AN_I2S_MODE_OUT) {
165- descr->dmatx_buf [0 ] = descr->dmatx_pool ->dequeue ( );
166- descr->dmatx_buf [1 ] = descr->dmatx_pool ->dequeue ( );
165+ descr->dmatx_buf [0 ] = descr->dmatx_pool ->alloc (DMA_BUFFER_READ );
166+ descr->dmatx_buf [1 ] = descr->dmatx_pool ->alloc (DMA_BUFFER_READ );
167167 tx_buf = (uint16_t *) descr->dmatx_buf [0 ]->data ();
168168 buf_size = descr->dmatx_buf [0 ]->size ();
169169 HAL_NVIC_DisableIRQ (descr->dmatx_irqn );
@@ -183,7 +183,7 @@ static int i2s_start_dma_transfer(i2s_descr_t *descr, i2s_mode_t i2s_mode) {
183183 return 0 ;
184184 }
185185 }
186-
186+ HAL_I2S_DMAPause (&descr-> i2s );
187187 // Re/enable DMA double buffer mode.
188188 if (i2s_mode & AN_I2S_MODE_IN) {
189189 hal_dma_enable_dbm (&descr->dmarx , descr->dmarx_buf [0 ]->data (), descr->dmarx_buf [1 ]->data ());
@@ -194,6 +194,7 @@ static int i2s_start_dma_transfer(i2s_descr_t *descr, i2s_mode_t i2s_mode) {
194194 hal_dma_enable_dbm (&descr->dmatx , descr->dmatx_buf [0 ]->data (), descr->dmatx_buf [1 ]->data ());
195195 HAL_NVIC_EnableIRQ (descr->dmatx_irqn );
196196 }
197+ HAL_I2S_DMAResume (&descr->i2s );
197198 return 1 ;
198199}
199200
@@ -216,7 +217,7 @@ DMABuffer<Sample> &AdvancedI2S::read() {
216217 while (!descr->dmarx_pool ->readable ()) {
217218 __WFI ();
218219 }
219- return *descr->dmarx_pool ->dequeue ( );
220+ return *descr->dmarx_pool ->alloc (DMA_BUFFER_READ );
220221 }
221222 return NULLBUF;
222223}
@@ -227,7 +228,7 @@ DMABuffer<Sample> &AdvancedI2S::dequeue() {
227228 while (!descr->dmatx_pool ->writable ()) {
228229 __WFI ();
229230 }
230- return *descr->dmatx_pool ->allocate ( );
231+ return *descr->dmatx_pool ->alloc (DMA_BUFFER_WRITE );
231232 }
232233 return NULLBUF;
233234}
@@ -241,7 +242,7 @@ void AdvancedI2S::write(DMABuffer<Sample> &dmabuf) {
241242
242243 // Make sure any cached data is flushed.
243244 dmabuf.flush ();
244- descr-> dmatx_pool -> enqueue (& dmabuf);
245+ dmabuf. release ( );
245246
246247 if (descr->dmatx_buf [0 ] == nullptr && (++buf_count % 3 ) == 0 ) {
247248 i2s_start_dma_transfer (descr, i2s_mode);
@@ -285,7 +286,7 @@ int AdvancedI2S::begin(i2s_mode_t i2s_mode, uint32_t sample_rate, size_t n_sampl
285286
286287 if (i2s_mode & AN_I2S_MODE_IN) {
287288 // Allocate DMA buffer pool.
288- descr->dmarx_pool = new DMABufferPool <Sample>(n_samples, 2 , n_buffers);
289+ descr->dmarx_pool = new DMAPool <Sample>(n_samples, 2 , n_buffers);
289290 if (descr->dmarx_pool == nullptr ) {
290291 descr = nullptr ;
291292 return 0 ;
@@ -299,7 +300,7 @@ int AdvancedI2S::begin(i2s_mode_t i2s_mode, uint32_t sample_rate, size_t n_sampl
299300
300301 if (i2s_mode & AN_I2S_MODE_OUT) {
301302 // Allocate DMA buffer pool.
302- descr->dmatx_pool = new DMABufferPool <Sample>(n_samples, 2 , n_buffers);
303+ descr->dmatx_pool = new DMAPool <Sample>(n_samples, 2 , n_buffers);
303304 if (descr->dmatx_pool == nullptr ) {
304305 descr = nullptr ;
305306 return 0 ;
@@ -358,7 +359,7 @@ void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *i2s) {
358359 // the next DMA memory address target.
359360 if (descr->dmatx_pool ->readable ()) {
360361 descr->dmatx_buf [ct]->release ();
361- descr->dmatx_buf [ct] = descr->dmatx_pool ->dequeue ( );
362+ descr->dmatx_buf [ct] = descr->dmatx_pool ->alloc (DMA_BUFFER_READ );
362363 hal_dma_update_memory (&descr->dmatx , descr->dmatx_buf [ct]->data ());
363364 } else {
364365 i2s_descr_deinit (descr, false );
@@ -384,15 +385,15 @@ void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *i2s) {
384385 // Make sure any cached data is discarded.
385386 descr->dmarx_buf [ct]->invalidate ();
386387 // Move current DMA buffer to ready queue.
387- descr->dmarx_pool -> enqueue (descr-> dmarx_buf [ct]);
388+ descr->dmarx_buf [ct]-> release ( );
388389 // Allocate a new free buffer.
389- descr->dmarx_buf [ct] = descr->dmarx_pool ->allocate ( );
390+ descr->dmarx_buf [ct] = descr->dmarx_pool ->alloc (DMA_BUFFER_WRITE );
390391 // Currently, all multi-channel buffers are interleaved.
391392 if (descr->dmarx_buf [ct]->channels () > 1 ) {
392- descr->dmarx_buf [ct]->setflags (DMA_BUFFER_INTRLVD);
393+ descr->dmarx_buf [ct]->set_flags (DMA_BUFFER_INTRLVD);
393394 }
394395 } else {
395- descr->dmarx_buf [ct]->setflags (DMA_BUFFER_DISCONT);
396+ descr->dmarx_buf [ct]->set_flags (DMA_BUFFER_DISCONT);
396397 }
397398
398399 // Update the next DMA target pointer.
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