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ARM: Better codegen for 64-bit compares.
This introduces a custom lowering for ISD::SETCCE (introduced in r253572) that allows us to emit a short code sequence for 64-bit compares. Before: push {r7, lr} cmp r0, r2 mov.w r0, #0 mov.w r12, #0 it hs movhs r0, #1 cmp r1, r3 it ge movge.w r12, #1 it eq moveq r12, r0 cmp.w r12, #0 bne .LBB1_2 @ BB#1: @ %bb1 bl f pop {r7, pc} .LBB1_2: @ %bb2 bl g pop {r7, pc} After: push {r7, lr} subs r0, r0, r2 sbcs.w r0, r1, r3 bge .LBB1_2 @ BB#1: @ %bb1 bl f pop {r7, pc} .LBB1_2: @ %bb2 bl g pop {r7, pc} Saves around 80KB in Chromium's libchrome.so. Some notes on this patch: - I don't much like the ARMISD::BRCOND and ARMISD::CMOV combines I introduced (nothing else needs them). However, they are necessary in order to avoid poor codegen, and they seem similar to existing combines in other backends (e.g. X86 combines (brcond (cmp (setcc Compare))) to (brcond Compare)). - No support for Thumb-1. This is in principle possible, but we'd need to implement ARMISD::SUBE for Thumb-1. Differential Revision: http://reviews.llvm.org/D15256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263962 91177308-0d34-0410-b5e6-96231b3b80d8
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5 files changed

+238
-144
lines changed

5 files changed

+238
-144
lines changed

‎lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -919,6 +919,10 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
919919
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
920920
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
921921

922+
// Thumb-1 cannot currently select ARMISD::SUBE.
923+
if (!Subtarget->isThumb1Only())
924+
setOperationAction(ISD::SETCCE, MVT::i32, Custom);
925+
922926
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
923927
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
924928
setOperationAction(ISD::BR_CC, MVT::f32, Custom);
@@ -4898,6 +4902,30 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
48984902
return Result;
48994903
}
49004904

4905+
static SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) {
4906+
SDValue LHS = Op.getOperand(0);
4907+
SDValue RHS = Op.getOperand(1);
4908+
SDValue Carry = Op.getOperand(2);
4909+
SDValue Cond = Op.getOperand(3);
4910+
SDLoc DL(Op);
4911+
4912+
assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
4913+
4914+
assert(Carry.getOpcode() != ISD::CARRY_FALSE);
4915+
SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
4916+
SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
4917+
4918+
SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
4919+
SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
4920+
SDValue ARMcc = DAG.getConstant(
4921+
IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
4922+
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4923+
SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
4924+
Cmp.getValue(1), SDValue());
4925+
return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
4926+
CCR, Chain.getValue(1));
4927+
}
4928+
49014929
/// isNEONModifiedImm - Check if the specified splat value corresponds to a
49024930
/// valid vector constant for a NEON instruction with a "modified immediate"
49034931
/// operand (e.g., VMOV). If so, return the encoded value.
@@ -7013,6 +7041,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
70137041
case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
70147042
case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
70157043
case ISD::SETCC: return LowerVSETCC(Op, DAG);
7044+
case ISD::SETCCE: return LowerSETCCE(Op, DAG);
70167045
case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
70177046
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
70187047
case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
@@ -10639,6 +10668,46 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
1063910668
return V;
1064010669
}
1064110670

10671+
/// PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
10672+
SDValue
10673+
ARMTargetLowering::PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const {
10674+
SDValue Cmp = N->getOperand(4);
10675+
if (Cmp.getOpcode() != ARMISD::CMPZ)
10676+
// Only looking at NE cases.
10677+
return SDValue();
10678+
10679+
EVT VT = N->getValueType(0);
10680+
SDLoc dl(N);
10681+
SDValue LHS = Cmp.getOperand(0);
10682+
SDValue RHS = Cmp.getOperand(1);
10683+
SDValue Chain = N->getOperand(0);
10684+
SDValue BB = N->getOperand(1);
10685+
SDValue ARMcc = N->getOperand(2);
10686+
ARMCC::CondCodes CC =
10687+
(ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
10688+
10689+
// (brcond Chain BB ne CPSR (cmpz (and (cmov 0 1 CC CPSR Cmp) 1) 0))
10690+
// -> (brcond Chain BB CC CPSR Cmp)
10691+
if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
10692+
LHS->getOperand(0)->getOpcode() == ARMISD::CMOV &&
10693+
LHS->getOperand(0)->hasOneUse()) {
10694+
auto *LHS00C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(0));
10695+
auto *LHS01C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(1));
10696+
auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
10697+
auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
10698+
if ((LHS00C && LHS00C->getZExtValue() == 0) &&
10699+
(LHS01C && LHS01C->getZExtValue() == 1) &&
10700+
(LHS1C && LHS1C->getZExtValue() == 1) &&
10701+
(RHSC && RHSC->getZExtValue() == 0)) {
10702+
return DAG.getNode(
10703+
ARMISD::BRCOND, dl, VT, Chain, BB, LHS->getOperand(0)->getOperand(2),
10704+
LHS->getOperand(0)->getOperand(3), LHS->getOperand(0)->getOperand(4));
10705+
}
10706+
}
10707+
10708+
return SDValue();
10709+
}
10710+
1064210711
/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
1064310712
SDValue
1064410713
ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
@@ -10692,6 +10761,21 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
1069210761
N->getOperand(3), NewCmp);
1069310762
}
1069410763

10764+
// (cmov F T ne CPSR (cmpz (cmov 0 1 CC CPSR Cmp) 0))
10765+
// -> (cmov F T CC CPSR Cmp)
10766+
if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
10767+
auto *LHS0C = dyn_cast<ConstantSDNode>(LHS->getOperand(0));
10768+
auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
10769+
auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
10770+
if ((LHS0C && LHS0C->getZExtValue() == 0) &&
10771+
(LHS1C && LHS1C->getZExtValue() == 1) &&
10772+
(RHSC && RHSC->getZExtValue() == 0)) {
10773+
return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
10774+
LHS->getOperand(2), LHS->getOperand(3),
10775+
LHS->getOperand(4));
10776+
}
10777+
}
10778+
1069510779
if (Res.getNode()) {
1069610780
APInt KnownZero, KnownOne;
1069710781
DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
@@ -10742,6 +10826,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
1074210826
case ISD::ZERO_EXTEND:
1074310827
case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
1074410828
case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
10829+
case ARMISD::BRCOND: return PerformBRCONDCombine(N, DCI.DAG);
1074510830
case ISD::LOAD: return PerformLOADCombine(N, DCI);
1074610831
case ARMISD::VLD2DUP:
1074710832
case ARMISD::VLD3DUP:

‎lib/Target/ARM/ARMISelLowering.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,7 @@ namespace llvm {
258258
SDNode *Node) const override;
259259

260260
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
261+
SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
261262
SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
262263
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
263264

‎test/CodeGen/ARM/atomic-64bit.ll‎

Lines changed: 72 additions & 96 deletions
Original file line numberDiff line numberDiff line change
@@ -251,43 +251,37 @@ define i64 @test10(i64* %ptr, i64 %val) {
251251
; CHECK-LABEL: test10:
252252
; CHECK: dmb {{ish$}}
253253
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
254-
; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
255-
; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
256254
; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
257-
; CHECK-LE: cmp [[REG1]], r1
258-
; CHECK-BE: cmp [[REG2]], r2
259-
; CHECK: movwls [[CARRY_LO]], #1
260-
; CHECK-LE: cmp [[REG2]], r2
261-
; CHECK-BE: cmp [[REG1]], r1
262-
; CHECK: movwle [[CARRY_HI]], #1
263-
; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
264-
; CHECK: cmp [[CARRY_HI]], #0
255+
; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
256+
; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
257+
; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
258+
; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
259+
; CHECK: mov [[CMP:[a-z0-9]+]], #0
260+
; CHECK: movwge [[CMP]], #1
261+
; CHECK: cmp [[CMP]], #0
265262
; CHECK: movne [[OUT_HI]], [[REG2]]
266263
; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
267264
; CHECK: movne [[OUT_LO]], [[REG1]]
268-
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
265+
; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
269266
; CHECK: cmp
270267
; CHECK: bne
271268
; CHECK: dmb {{ish$}}
272269

273270
; CHECK-THUMB-LABEL: test10:
274271
; CHECK-THUMB: dmb {{ish$}}
275272
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
276-
; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+|lr]], #0
277-
; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+|lr]], #0
278-
; CHECK-THUMB-LE: cmp [[REG1]], r2
279-
; CHECK-THUMB-BE: cmp [[REG2]], r3
280-
; CHECK-THUMB: movls.w [[CARRY_LO]], #1
281-
; CHECK-THUMB-LE: cmp [[REG2]], r3
282-
; CHECK-THUMB-BE: cmp [[REG1]], r2
283-
; CHECK-THUMB: movle [[CARRY_HI]], #1
284-
; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
285-
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
286-
; CHECK-THUMB: cmp [[CARRY_HI]], #0
287-
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
273+
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
274+
; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
275+
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
276+
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
277+
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
278+
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
279+
; CHECK-THUMB: movge.w [[CMP]], #1
280+
; CHECK-THUMB: cmp.w [[CMP]], #0
281+
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
288282
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
289283
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
290-
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
284+
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
291285
; CHECK-THUMB: cmp
292286
; CHECK-THUMB: bne
293287
; CHECK-THUMB: dmb {{ish$}}
@@ -300,43 +294,37 @@ define i64 @test11(i64* %ptr, i64 %val) {
300294
; CHECK-LABEL: test11:
301295
; CHECK: dmb {{ish$}}
302296
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
303-
; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
304-
; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
305297
; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
306-
; CHECK-LE: cmp [[REG1]], r1
307-
; CHECK-BE: cmp [[REG2]], r2
308-
; CHECK: movwls [[CARRY_LO]], #1
309-
; CHECK-LE: cmp [[REG2]], r2
310-
; CHECK-BE: cmp [[REG1]], r1
311-
; CHECK: movwls [[CARRY_HI]], #1
312-
; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
313-
; CHECK: cmp [[CARRY_HI]], #0
298+
; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
299+
; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
300+
; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
301+
; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
302+
; CHECK: mov [[CMP:[a-z0-9]+]], #0
303+
; CHECK: movwhs [[CMP]], #1
304+
; CHECK: cmp [[CMP]], #0
314305
; CHECK: movne [[OUT_HI]], [[REG2]]
315306
; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
316307
; CHECK: movne [[OUT_LO]], [[REG1]]
317-
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
308+
; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
318309
; CHECK: cmp
319310
; CHECK: bne
320311
; CHECK: dmb {{ish$}}
321312

322313
; CHECK-THUMB-LABEL: test11:
323314
; CHECK-THUMB: dmb {{ish$}}
324315
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
325-
; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
326-
; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
327-
; CHECK-THUMB-LE: cmp [[REG1]], r2
328-
; CHECK-THUMB-BE: cmp [[REG2]], r3
329-
; CHECK-THUMB: movls.w [[CARRY_LO]], #1
330-
; CHECK-THUMB-LE: cmp [[REG2]], r3
331-
; CHECK-THUMB-BE: cmp [[REG1]], r2
332-
; CHECK-THUMB: movls [[CARRY_HI]], #1
333-
; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
334-
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
335-
; CHECK-THUMB: cmp [[CARRY_HI]], #0
336-
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
316+
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
317+
; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
318+
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
319+
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
320+
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
321+
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
322+
; CHECK-THUMB: movhs.w [[CMP]], #1
323+
; CHECK-THUMB: cmp.w [[CMP]], #0
324+
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
337325
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
338326
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
339-
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
327+
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
340328
; CHECK-THUMB: cmp
341329
; CHECK-THUMB: bne
342330
; CHECK-THUMB: dmb {{ish$}}
@@ -349,43 +337,37 @@ define i64 @test12(i64* %ptr, i64 %val) {
349337
; CHECK-LABEL: test12:
350338
; CHECK: dmb {{ish$}}
351339
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
352-
; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
353-
; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
354340
; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
355-
; CHECK-LE: cmp [[REG1]], r1
356-
; CHECK-BE: cmp [[REG2]], r2
357-
; CHECK: movwhi [[CARRY_LO]], #1
358-
; CHECK-LE: cmp [[REG2]], r2
359-
; CHECK-BE: cmp [[REG1]], r1
360-
; CHECK: movwgt [[CARRY_HI]], #1
361-
; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
362-
; CHECK: cmp [[CARRY_HI]], #0
341+
; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
342+
; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
343+
; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
344+
; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
345+
; CHECK: mov [[CMP:[a-z0-9]+]], #0
346+
; CHECK: movwlt [[CMP]], #1
347+
; CHECK: cmp [[CMP]], #0
363348
; CHECK: movne [[OUT_HI]], [[REG2]]
364349
; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
365350
; CHECK: movne [[OUT_LO]], [[REG1]]
366-
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
351+
; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
367352
; CHECK: cmp
368353
; CHECK: bne
369354
; CHECK: dmb {{ish$}}
370355

371356
; CHECK-THUMB-LABEL: test12:
372357
; CHECK-THUMB: dmb {{ish$}}
373358
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
374-
; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
375-
; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
376-
; CHECK-THUMB-LE: cmp [[REG1]], r2
377-
; CHECK-THUMB-BE: cmp [[REG2]], r3
378-
; CHECK-THUMB: movhi.w [[CARRY_LO]], #1
379-
; CHECK-THUMB-LE: cmp [[REG2]], r3
380-
; CHECK-THUMB-BE: cmp [[REG1]], r2
381-
; CHECK-THUMB: movgt [[CARRY_HI]], #1
382-
; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
383-
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
384-
; CHECK-THUMB: cmp [[CARRY_HI]], #0
385-
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
359+
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
360+
; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
361+
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
362+
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
363+
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
364+
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
365+
; CHECK-THUMB: movlt.w [[CMP]], #1
366+
; CHECK-THUMB: cmp.w [[CMP]], #0
367+
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
386368
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
387369
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
388-
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
370+
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
389371
; CHECK-THUMB: cmp
390372
; CHECK-THUMB: bne
391373
; CHECK-THUMB: dmb {{ish$}}
@@ -398,43 +380,37 @@ define i64 @test13(i64* %ptr, i64 %val) {
398380
; CHECK-LABEL: test13:
399381
; CHECK: dmb {{ish$}}
400382
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
401-
; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
402-
; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
403383
; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
404-
; CHECK-LE: cmp [[REG1]], r1
405-
; CHECK-BE: cmp [[REG2]], r2
406-
; CHECK: movwhi [[CARRY_LO]], #1
407-
; CHECK-LE: cmp [[REG2]], r2
408-
; CHECK-BE: cmp [[REG1]], r1
409-
; CHECK: movwhi [[CARRY_HI]], #1
410-
; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
411-
; CHECK: cmp [[CARRY_HI]], #0
384+
; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
385+
; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
386+
; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
387+
; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
388+
; CHECK: mov [[CMP:[a-z0-9]+]], #0
389+
; CHECK: movwlo [[CMP]], #1
390+
; CHECK: cmp [[CMP]], #0
412391
; CHECK: movne [[OUT_HI]], [[REG2]]
413392
; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
414393
; CHECK: movne [[OUT_LO]], [[REG1]]
415-
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
394+
; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
416395
; CHECK: cmp
417396
; CHECK: bne
418397
; CHECK: dmb {{ish$}}
419398

420399
; CHECK-THUMB-LABEL: test13:
421400
; CHECK-THUMB: dmb {{ish$}}
422401
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
423-
; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
424-
; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
425-
; CHECK-THUMB-LE: cmp [[REG1]], r2
426-
; CHECK-THUMB-BE: cmp [[REG2]], r3
427-
; CHECK-THUMB: movhi.w [[CARRY_LO]], #1
428-
; CHECK-THUMB-LE: cmp [[REG2]], r3
429-
; CHECK-THUMB-BE: cmp [[REG1]], r2
430-
; CHECK-THUMB: movhi [[CARRY_HI]], #1
431-
; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
432-
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
433-
; CHECK-THUMB: cmp [[CARRY_HI]], #0
434-
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
402+
; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
403+
; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
404+
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
405+
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
406+
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
407+
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
408+
; CHECK-THUMB: movlo.w [[CMP]], #1
409+
; CHECK-THUMB: cmp.w [[CMP]], #0
410+
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
435411
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
436412
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
437-
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
413+
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
438414
; CHECK-THUMB: cmp
439415
; CHECK-THUMB: bne
440416
; CHECK-THUMB: dmb {{ish$}}

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