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[X86][SSE41] Combine vector blends with zero
Part 2 of 2 This patch add support for combining target shuffles into blends-with-zero. Differential Revision: http://reviews.llvm.org/D17483 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261745 91177308-0d34-0410-b5e6-96231b3b80d8
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7 files changed

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‎lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4332,6 +4332,17 @@ static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
43324332
return true;
43334333
}
43344334

4335+
/// Return true if every element in Mask, beginning
4336+
/// from position Pos and ending in Pos+Size, falls within the specified
4337+
/// sequential range (Low, Low+Size], or is undef or is zero.
4338+
static bool isSequentialOrUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
4339+
unsigned Size, int Low) {
4340+
for (unsigned i = Pos, e = Pos + Size; i != e; ++i, ++Low)
4341+
if (!isUndefOrZero(Mask[i]) && Mask[i] != Low)
4342+
return false;
4343+
return true;
4344+
}
4345+
43354346
/// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
43364347
/// extract that is suitable for instruction that extract 128 or 256 bit vectors
43374348
static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
@@ -23666,6 +23677,53 @@ static bool combineX86ShuffleChain(SDValue Input, SDValue Root,
2366623677
return true;
2366723678
}
2366823679

23680+
// Attempt to blend with zero.
23681+
if (VT.getVectorNumElements() <= 8 &&
23682+
((Subtarget.hasSSE41() && VT.is128BitVector()) ||
23683+
(Subtarget.hasAVX() && VT.is256BitVector()))) {
23684+
// Convert VT to a type compatible with X86ISD::BLENDI.
23685+
// TODO - add 16i16 support (requires lane duplication).
23686+
MVT ShuffleVT = VT;
23687+
if (Subtarget.hasAVX2()) {
23688+
if (VT == MVT::v4i64)
23689+
ShuffleVT = MVT::v8i32;
23690+
else if (VT == MVT::v2i64)
23691+
ShuffleVT = MVT::v4i32;
23692+
} else {
23693+
if (VT == MVT::v2i64 || VT == MVT::v4i32)
23694+
ShuffleVT = MVT::v8i16;
23695+
else if (VT == MVT::v4i64)
23696+
ShuffleVT = MVT::v4f64;
23697+
else if (VT == MVT::v8i32)
23698+
ShuffleVT = MVT::v8f32;
23699+
}
23700+
23701+
if (isSequentialOrUndefOrZeroInRange(Mask, /*Pos*/ 0, /*Size*/ Mask.size(),
23702+
/*Low*/ 0) &&
23703+
Mask.size() <= ShuffleVT.getVectorNumElements()) {
23704+
unsigned BlendMask = 0;
23705+
unsigned ShuffleSize = ShuffleVT.getVectorNumElements();
23706+
unsigned MaskRatio = ShuffleSize / Mask.size();
23707+
23708+
for (unsigned i = 0; i != ShuffleSize; ++i)
23709+
if (Mask[i / MaskRatio] < 0)
23710+
BlendMask |= 1u << i;
23711+
23712+
if (Root.getOpcode() != X86ISD::BLENDI ||
23713+
Root->getConstantOperandVal(2) != BlendMask) {
23714+
SDValue Zero = getZeroVector(ShuffleVT, Subtarget, DAG, DL);
23715+
Res = DAG.getBitcast(ShuffleVT, Input);
23716+
DCI.AddToWorklist(Res.getNode());
23717+
Res = DAG.getNode(X86ISD::BLENDI, DL, ShuffleVT, Res, Zero,
23718+
DAG.getConstant(BlendMask, DL, MVT::i8));
23719+
DCI.AddToWorklist(Res.getNode());
23720+
DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Res),
23721+
/*AddTo*/ true);
23722+
return true;
23723+
}
23724+
}
23725+
}
23726+
2366923727
// Don't try to re-form single instruction chains under any circumstances now
2367023728
// that we've done encoding canonicalization for them.
2367123729
if (Depth < 2)

‎test/CodeGen/X86/insertelement-zero.ll‎

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -75,8 +75,7 @@ define <4 x double> @insert_v4f64_0zz3(<4 x double> %a) {
7575
; AVX-LABEL: insert_v4f64_0zz3:
7676
; AVX: # BB#0:
7777
; AVX-NEXT: vxorpd %ymm1, %ymm1, %ymm1
78-
; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3]
79-
; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3]
78+
; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3]
8079
; AVX-NEXT: retq
8180
%1 = insertelement <4 x double> %a, double 0.0, i32 1
8281
%2 = insertelement <4 x double> %1, double 0.0, i32 2
@@ -235,8 +234,7 @@ define <8 x float> @insert_v8f32_z12345z7(<8 x float> %a) {
235234
; AVX-LABEL: insert_v8f32_z12345z7:
236235
; AVX: # BB#0:
237236
; AVX-NEXT: vxorps %ymm1, %ymm1, %ymm1
238-
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7]
239-
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6],ymm0[7]
237+
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
240238
; AVX-NEXT: retq
241239
%1 = insertelement <8 x float> %a, float 0.0, i32 0
242240
%2 = insertelement <8 x float> %1, float 0.0, i32 6
@@ -330,15 +328,13 @@ define <8 x i32> @insert_v8i32_z12345z7(<8 x i32> %a) {
330328
; AVX1-LABEL: insert_v8i32_z12345z7:
331329
; AVX1: # BB#0:
332330
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1
333-
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7]
334-
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6],ymm0[7]
331+
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
335332
; AVX1-NEXT: retq
336333
;
337334
; AVX2-LABEL: insert_v8i32_z12345z7:
338335
; AVX2: # BB#0:
339336
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1
340-
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7]
341-
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6],ymm0[7]
337+
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
342338
; AVX2-NEXT: retq
343339
%1 = insertelement <8 x i32> %a, i32 0, i32 0
344340
%2 = insertelement <8 x i32> %1, i32 0, i32 6
@@ -370,15 +366,13 @@ define <8 x i16> @insert_v8i16_z12345z7(<8 x i16> %a) {
370366
; SSE41-LABEL: insert_v8i16_z12345z7:
371367
; SSE41: # BB#0:
372368
; SSE41-NEXT: pxor %xmm1, %xmm1
373-
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]
374-
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6],xmm0[7]
369+
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5],xmm1[6],xmm0[7]
375370
; SSE41-NEXT: retq
376371
;
377372
; AVX-LABEL: insert_v8i16_z12345z7:
378373
; AVX: # BB#0:
379374
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
380-
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]
381-
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6],xmm0[7]
375+
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5],xmm1[6],xmm0[7]
382376
; AVX-NEXT: retq
383377
%1 = insertelement <8 x i16> %a, i16 0, i32 0
384378
%2 = insertelement <8 x i16> %1, i16 0, i32 6
@@ -413,8 +407,7 @@ define <16 x i16> @insert_v16i16_z12345z789ABZDEz(<16 x i16> %a) {
413407
; SSE41-LABEL: insert_v16i16_z12345z789ABZDEz:
414408
; SSE41: # BB#0:
415409
; SSE41-NEXT: pxor %xmm2, %xmm2
416-
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3,4,5,6,7]
417-
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm2[6],xmm0[7]
410+
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3,4,5],xmm2[6],xmm0[7]
418411
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6],xmm2[7]
419412
; SSE41-NEXT: retq
420413
;

‎test/CodeGen/X86/insertps-combine.ll‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -117,12 +117,14 @@ define <4 x float> @insertps_undef_input0(<4 x float> %a0, <4 x float> %a1) {
117117
define <4 x float> @insertps_undef_input1(<4 x float> %a0, <4 x float> %a1) {
118118
; SSE-LABEL: insertps_undef_input1:
119119
; SSE: # BB#0:
120-
; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[3]
120+
; SSE-NEXT: xorps %xmm1, %xmm1
121+
; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
121122
; SSE-NEXT: retq
122123
;
123124
; AVX-LABEL: insertps_undef_input1:
124125
; AVX: # BB#0:
125-
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[3]
126+
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
127+
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
126128
; AVX-NEXT: retq
127129
%res0 = fadd <4 x float> %a1, <float 1.0, float 1.0, float 1.0, float 1.0>
128130
%res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %res0, i8 21)

‎test/CodeGen/X86/merge-consecutive-loads-256.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -278,8 +278,8 @@ define <8 x float> @merge_8f32_2f32_23z5(<2 x float>* %ptr) nounwind uwtable noi
278278
; X32-AVX-LABEL: merge_8f32_2f32_23z5:
279279
; X32-AVX: # BB#0:
280280
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
281-
; X32-AVX-NEXT: vxorpd %ymm0, %ymm0, %ymm0
282-
; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3]
281+
; X32-AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0
282+
; X32-AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3],ymm0[4,5],mem[6,7]
283283
; X32-AVX-NEXT: retl
284284
%ptr0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 2
285285
%ptr1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3

‎test/CodeGen/X86/vec_insert-7.ll‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,9 @@ define x86_mmx @mmx_movzl(x86_mmx %x) nounwind {
1212
; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
1313
; CHECK-NEXT: movl $32, %eax
1414
; CHECK-NEXT: pinsrd $0, %eax, %xmm0
15-
; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
16-
; CHECK-NEXT: movq %xmm0, (%esp)
15+
; CHECK-NEXT: pxor %xmm1, %xmm1
16+
; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
17+
; CHECK-NEXT: movq %xmm1, (%esp)
1718
; CHECK-NEXT: movq (%esp), %mm0
1819
; CHECK-NEXT: addl $20, %esp
1920
; CHECK-NEXT: retl

‎test/CodeGen/X86/vector-shuffle-128-v2.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -932,15 +932,15 @@ define <2 x i64> @shuffle_v2i64_bitcast_z123(<2 x i64> %x) {
932932
; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
933933
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
934934
; SSE41-NEXT: xorps %xmm1, %xmm1
935-
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
935+
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
936936
; SSE41-NEXT: retq
937937
;
938938
; AVX1-LABEL: shuffle_v2i64_bitcast_z123:
939939
; AVX1: # BB#0:
940940
; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
941941
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
942942
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
943-
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
943+
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
944944
; AVX1-NEXT: retq
945945
;
946946
; AVX2-LABEL: shuffle_v2i64_bitcast_z123:

‎test/CodeGen/X86/vector-zext.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1162,8 +1162,8 @@ define <4 x i64> @shuf_zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone
11621162
; AVX1-LABEL: shuf_zext_4i32_to_4i64:
11631163
; AVX1: # BB#0: # %entry
11641164
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero
1165-
; AVX1-NEXT: vxorpd %xmm2, %xmm2, %xmm2
1166-
; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
1165+
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
1166+
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
11671167
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,0]
11681168
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
11691169
; AVX1-NEXT: retq
@@ -1592,8 +1592,8 @@ define <4 x i64> @shuf_zext_4i32_to_4i64_offset1(<4 x i32> %A) nounwind uwtable
15921592
; AVX1-LABEL: shuf_zext_4i32_to_4i64_offset1:
15931593
; AVX1: # BB#0: # %entry
15941594
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[3],zero,zero,zero
1595-
; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2
1596-
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0,1],xmm0[2],xmm2[3]
1595+
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
1596+
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5],xmm2[6,7]
15971597
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
15981598
; AVX1-NEXT: retq
15991599
;

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